From mboxrd@z Thu Jan  1 00:00:00 1970
From: Matt Wilson <msw@amazon.com>
Subject: Re: [PATCH] xen/x86: Add support for cpuid masking on
 Intel Xeon Processor E5 Family
Date: Tue, 7 Aug 2012 10:47:33 -0700
Message-ID: <20120807174733.GA5592@US-SEA-R8XVZTX>
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To: Jan Beulich <JBeulich@suse.com>
Cc: Jinsong Liu <jinsong.liu@intel.com>, Keir Fraser <keir@xen.org>, Donald D Dugger <donald.d.dugger@intel.com>, Jun Nakajima <jun.nakajima@intel.com>, "xen-devel@lists.xen.org" <xen-devel@lists.xen.org>
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On Mon, Aug 06, 2012 at 11:49:12PM -0700, Jan Beulich wrote:
> >>> On 06.08.12 at 22:23, "Nakajima, Jun" <jun.nakajima@intel.com> wrote:
> > On Sun, Jul 29, 2012 at 11:57 PM, Jan Beulich <JBeulich@suse.com> wrote:
> > 
> >> >>> On 28.07.12 at 21:19, Matt Wilson <msw@amazon.com> wrote:
> >> > Although the "Intel Virtualization Technology FlexMigration
> >> > Application Note" (http://www.intel.com/Assets/PDF/manual/323850.pdf)
> >> > does not document support for extended model 2H model DH (Intel Xeon
> >> > Processor E5 Family), empirical evidence shows that the same MSR
> >> > addresses can be used for cpuid masking as exdended model 2H model AH
> >> > (Intel Xen Processor E3-1200 Family).
> >>
> >> Empirical evidence isn't really enough - let's have someone at Intel
> >> confirm this - Jun, Don?
> >>
> > 
> > Thanks for the patch. The patch looks good, and it should be in.
> > We'll update the document.
> 
> I take this as an ack then, and will commit it that way.

Thanks for committing, Jan.

For what it's worth, I think that the first line of the commit log got
dropped, which makes for a strange short log message of:

  Although the "Intel Virtualization Technology FlexMigration

Matt

> >> > Signed-off-by: Matt Wilson <msw@amazon.com>
> >> >
> >> > diff -r e6266fc76d08 -r bf922651da96 xen/arch/x86/cpu/intel.c
> >> > --- a/xen/arch/x86/cpu/intel.c        Fri Jul 27 12:22:13 2012 +0200
> >> > +++ b/xen/arch/x86/cpu/intel.c        Sat Jul 28 17:27:30 2012 +0000
> >> > @@ -104,7 +104,7 @@ static void __devinit set_cpuidmask(cons
> >> >                       return;
> >> >               extra = "xsave ";
> >> >               break;
> >> > -     case 0x2a:
> >> > +     case 0x2a: case 0x2d:
> >> >               wrmsr(MSR_INTEL_CPUID1_FEATURE_MASK_V2,
> >> >                     opt_cpuid_mask_ecx,
> >> >                     opt_cpuid_mask_edx);
> >>
> >>
> >>
> >>
> > 
> > 
> 
>