From: Alan Cox <alan@lxorguk.ukuu.org.uk>
To: airlied@linux.ie, dri-devel@lists.freedesktop.org
Subject: [PATCH 1/8] Fix incorrect SR issue when disabling CRTC already in disabled state
Date: Wed, 08 Aug 2012 14:53:15 +0100 [thread overview]
Message-ID: <20120808135225.974.25210.stgit@bluebook> (raw)
From: Zhao Yakui <yakui.zhao@intel.com>
Currently when trying to call the DPMS off again for one CRTC with DPMS off,
it will firstly disable the SR and can't enable it again because of the
incorrect check/logic. In such case the self refresh is still disabled
although one CRTC pipe is active. This is wrong.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
[Ported to in kernel driver]
Signed-off-by: Alan Cox <alan@linux.intel.com>
---
drivers/gpu/drm/gma500/cdv_intel_display.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/gma500/cdv_intel_display.c b/drivers/gpu/drm/gma500/cdv_intel_display.c
index a68509b..5c3a312 100644
--- a/drivers/gpu/drm/gma500/cdv_intel_display.c
+++ b/drivers/gpu/drm/gma500/cdv_intel_display.c
@@ -791,7 +791,7 @@ static void cdv_intel_crtc_dpms(struct drm_crtc *crtc, int mode)
case DRM_MODE_DPMS_STANDBY:
case DRM_MODE_DPMS_SUSPEND:
if (psb_intel_crtc->active)
- return;
+ break;
psb_intel_crtc->active = true;
@@ -835,7 +835,6 @@ static void cdv_intel_crtc_dpms(struct drm_crtc *crtc, int mode)
REG_WRITE(map->status, temp);
REG_READ(map->status);
- cdv_intel_update_watermark(dev, crtc);
cdv_intel_crtc_load_lut(crtc);
/* Give the overlay scaler a chance to enable
@@ -845,7 +844,7 @@ static void cdv_intel_crtc_dpms(struct drm_crtc *crtc, int mode)
break;
case DRM_MODE_DPMS_OFF:
if (!psb_intel_crtc->active)
- return;
+ break;
psb_intel_crtc->active = false;
@@ -892,10 +891,10 @@ static void cdv_intel_crtc_dpms(struct drm_crtc *crtc, int mode)
/* Wait for the clocks to turn off. */
udelay(150);
- cdv_intel_update_watermark(dev, crtc);
psb_intel_crtc->crtc_enable = false;
break;
}
+ cdv_intel_update_watermark(dev, crtc);
/*Set FIFO Watermarks*/
REG_WRITE(DSPARB, 0x3F3E);
}
next reply other threads:[~2012-08-08 12:55 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-08-08 13:53 Alan Cox [this message]
2012-08-08 13:53 ` [PATCH 2/8] Program the DPLL lane based on the selected digitial port Alan Cox
2012-08-08 13:54 ` [PATCH 3/8] From: Zhao Yakui <yakui.zhao@intel.com> Alan Cox
2012-08-08 13:54 ` [PATCH 4/8] cdv: add the bits that don't need the new code Alan Cox
2012-08-08 13:55 ` [PATCH 5/8] cdv: sync up and add the displayport code to the build Alan Cox
2012-08-08 13:55 ` [PATCH 6/8] cdv: enable the DisplayPort support Alan Cox
2012-08-08 13:55 ` [PATCH 7/8] cdv: Add eDP support Alan Cox
2012-08-08 13:57 ` [PATCH 8/8] From: Zhao Yakui <yakui.zhao@intel.com> Alan Cox
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