From: Andi Kleen <andi@firstfloor.org>
To: Stephane Eranian <eranian@google.com>
Cc: linux-kernel@vger.kernel.org, peterz@infradead.org,
mingo@elte.hu, andi@firstfloor.org, zheng.z.yan@intel.com
Subject: Re: [PATCH] perf/x86: enable Intel Cedarview Atom suppport
Date: Mon, 20 Aug 2012 11:41:38 +0200 [thread overview]
Message-ID: <20120820094138.GA16230@one.firstfloor.org> (raw)
In-Reply-To: <20120820092421.GA11284@quad>
> diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
> index 7f2739e..0d3d63a 100644
> --- a/arch/x86/kernel/cpu/perf_event_intel.c
> +++ b/arch/x86/kernel/cpu/perf_event_intel.c
> @@ -2008,6 +2008,7 @@ __init int intel_pmu_init(void)
> break;
>
> case 28: /* Atom */
> + case 54: /* Cedariew */
Ack. We currently miss some more 32nm Atoms too, will send patches soon.
> memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
> sizeof(hw_cache_event_ids));
>
> diff --git a/arch/x86/kernel/cpu/perf_event_intel_lbr.c b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
> index 520b426..da02e9c 100644
> --- a/arch/x86/kernel/cpu/perf_event_intel_lbr.c
> +++ b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
> @@ -686,7 +686,8 @@ void intel_pmu_lbr_init_atom(void)
> * to have an operational LBR which can freeze
> * on PMU interrupt
> */
> - if (boot_cpu_data.x86_mask < 10) {
> + if (boot_cpu_data.x86_model == 28
> + && boot_cpu_data.x86_mask < 10) {
Is that correct?
-Andi
--
ak@linux.intel.com -- Speaking for myself only.
next prev parent reply other threads:[~2012-08-20 9:41 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-08-20 9:24 [PATCH] perf/x86: enable Intel Cedarview Atom suppport Stephane Eranian
2012-08-20 9:41 ` Andi Kleen [this message]
2012-08-20 10:06 ` Stephane Eranian
2012-09-04 18:52 ` [tip:perf/urgent] perf/x86: Enable " tip-bot for Stephane Eranian
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