Re: [PATCH 4/5] ARM: OMAP4: Add L2 Cache Controller in Device Tree

[Felipe Balbi <balbi@ti.com>]

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On Mon, Aug 20, 2012 at 03:51:43PM +0200, Benoit Cousson wrote:
> > +		compatible = "arm,pl310-cache";
> > +		reg = <0x48242000 0x1000>;
> > +		cache-unified;
> > +		cache-level = <2>;
> > +	};
> > +
> 
> In theory, the L2 cache should be referenced from the CPUs.
> 
> Here is the way it is done for mpc8541cdc.dts for example:
> 
> 	cpus {
> 		#address-cells = <1>;
> 		#size-cells = <0>;
> 
> 		PowerPC,8541@0 {
> 			device_type = "cpu";
> 			reg = <0x0>;
> 			d-cache-line-size = <32>;	// 32 bytes
> 			i-cache-line-size = <32>;	// 32 bytes
> 			d-cache-size = <0x8000>;		// L1, 32K
> 			i-cache-size = <0x8000>;		// L1, 32K
> 			timebase-frequency = <0>;	//  33 MHz, from uboot
> 			bus-frequency = <0>;	// 166 MHz
> 			clock-frequency = <0>;	// 825 MHz, from uboot
> 			next-level-cache = <&L2>;
> 		};
> 	};
> 
> ...
> 
> 		L2: l2-cache-controller@20000 {
> 			compatible = "fsl,mpc8541-l2-cache-controller";
> 			reg = <0x20000 0x1000>;
> 			cache-line-size = <32>;	// 32 bytes
> 			cache-size = <0x40000>;	// L2, 256K
> 			interrupt-parent = <&mpic>;
> 			interrupts = <16 2>;
> 		};

that's actually outside of the cpus {} block.

-- 
balbi

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