From: Aurelien Jarno <aurelien@aurel32.net>
To: Jia Liu <proljc@gmail.com>
Cc: qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH v6 02/13] target-mips-ase-dsp: Use correct acc value to index cpu_HI/cpu_LO rather than using a fix number
Date: Thu, 23 Aug 2012 15:33:05 +0200 [thread overview]
Message-ID: <20120823133305.GC3553@ohm.aurel32.net> (raw)
In-Reply-To: <1345531999-17872-3-git-send-email-proljc@gmail.com>
On Tue, Aug 21, 2012 at 02:53:08PM +0800, Jia Liu wrote:
> Use correct acc value to index cpu_HI/cpu_LO rather than using a fix number.
>
> Signed-off-by: Jia Liu <proljc@gmail.com>
> ---
> target-mips/translate.c | 107 +++++++++++++++++++++++++++++++++++------------
> 1 file changed, 81 insertions(+), 26 deletions(-)
This code assume that the DSP ASE is always available and enabled, while
when it is not the case, it should trigger an exception.
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index 47daf85..0793153 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -5,6 +5,7 @@
> * Copyright (c) 2006 Marius Groeger (FPU operations)
> * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
> * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support)
> + * Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support)
> *
> * This library is free software; you can redistribute it and/or
> * modify it under the terms of the GNU Lesser General Public
> @@ -1972,6 +1973,7 @@ static void gen_shift (CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
> static void gen_HILO (DisasContext *ctx, uint32_t opc, int reg)
> {
> const char *opn = "hilo";
> + unsigned int acc;
>
> if (reg == 0 && (opc == OPC_MFHI || opc == OPC_MFLO)) {
> /* Treat as NOP. */
> @@ -1980,25 +1982,71 @@ static void gen_HILO (DisasContext *ctx, uint32_t opc, int reg)
> }
> switch (opc) {
> case OPC_MFHI:
> - tcg_gen_mov_tl(cpu_gpr[reg], cpu_HI[0]);
> + acc = ((ctx->opcode) >> 21) & 0x03;
> +#if defined(TARGET_MIPS64)
> + if (acc == 0) {
> + tcg_gen_mov_tl(cpu_gpr[reg], cpu_HI[acc]);
> + } else {
> + tcg_gen_ext32s_tl(cpu_gpr[reg], cpu_HI[acc]);
> + }
> +#else
> + tcg_gen_mov_tl(cpu_gpr[reg], cpu_HI[acc]);
> +#endif
> opn = "mfhi";
> break;
> case OPC_MFLO:
> - tcg_gen_mov_tl(cpu_gpr[reg], cpu_LO[0]);
> + acc = ((ctx->opcode) >> 21) & 0x03;
> +#if defined(TARGET_MIPS64)
> + if (acc == 0) {
> + tcg_gen_mov_tl(cpu_gpr[reg], cpu_LO[acc]);
> + } else {
> + tcg_gen_ext32s_tl(cpu_gpr[reg], cpu_LO[acc]);
> + }
> +#else
> + tcg_gen_mov_tl(cpu_gpr[reg], cpu_LO[acc]);
> +#endif
> opn = "mflo";
> break;
> case OPC_MTHI:
> - if (reg != 0)
> - tcg_gen_mov_tl(cpu_HI[0], cpu_gpr[reg]);
> - else
> - tcg_gen_movi_tl(cpu_HI[0], 0);
> + acc = ((ctx->opcode) >> 11) & 0x03;
> +#if defined(TARGET_MIPS64)
> + if (reg != 0) {
> + if (acc == 0) {
> + tcg_gen_mov_tl(cpu_HI[acc], cpu_gpr[reg]);
> + } else {
> + tcg_gen_ext32s_tl(cpu_HI[acc], cpu_gpr[reg]);
> + }
> + } else {
> + tcg_gen_movi_tl(cpu_HI[acc], 0);
> + }
> +#else
> + if (reg != 0) {
> + tcg_gen_mov_tl(cpu_HI[acc], cpu_gpr[reg]);
> + } else {
> + tcg_gen_movi_tl(cpu_HI[acc], 0);
> + }
> +#endif
> opn = "mthi";
> break;
> case OPC_MTLO:
> - if (reg != 0)
> - tcg_gen_mov_tl(cpu_LO[0], cpu_gpr[reg]);
> - else
> - tcg_gen_movi_tl(cpu_LO[0], 0);
> + acc = ((ctx->opcode) >> 11) & 0x03;
> +#if defined(TARGET_MIPS64)
> + if (reg != 0) {
> + if (acc == 0) {
> + tcg_gen_mov_tl(cpu_LO[acc], cpu_gpr[reg]);
> + } else {
> + tcg_gen_ext32s_tl(cpu_LO[acc], cpu_gpr[reg]);
> + }
> + } else {
> + tcg_gen_movi_tl(cpu_LO[acc], 0);
> + }
> +#else
> + if (reg != 0) {
> + tcg_gen_mov_tl(cpu_LO[acc], cpu_gpr[reg]);
> + } else {
> + tcg_gen_movi_tl(cpu_LO[acc], 0);
> + }
> +#endif
> opn = "mtlo";
> break;
> }
> @@ -2011,6 +2059,7 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
> {
> const char *opn = "mul/div";
> TCGv t0, t1;
> + unsigned int acc;
>
> switch (opc) {
> case OPC_DIV:
> @@ -2073,6 +2122,7 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
> {
> TCGv_i64 t2 = tcg_temp_new_i64();
> TCGv_i64 t3 = tcg_temp_new_i64();
> + acc = ((ctx->opcode) >> 11) & 0x03;
>
> tcg_gen_ext_tl_i64(t2, t0);
> tcg_gen_ext_tl_i64(t3, t1);
> @@ -2082,8 +2132,8 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
> tcg_gen_shri_i64(t2, t2, 32);
> tcg_gen_trunc_i64_tl(t1, t2);
> tcg_temp_free_i64(t2);
> - tcg_gen_ext32s_tl(cpu_LO[0], t0);
> - tcg_gen_ext32s_tl(cpu_HI[0], t1);
> + tcg_gen_ext32s_tl(cpu_LO[acc], t0);
> + tcg_gen_ext32s_tl(cpu_HI[acc], t1);
> }
> opn = "mult";
> break;
> @@ -2091,6 +2141,7 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
> {
> TCGv_i64 t2 = tcg_temp_new_i64();
> TCGv_i64 t3 = tcg_temp_new_i64();
> + acc = ((ctx->opcode) >> 11) & 0x03;
>
> tcg_gen_ext32u_tl(t0, t0);
> tcg_gen_ext32u_tl(t1, t1);
> @@ -2102,8 +2153,8 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
> tcg_gen_shri_i64(t2, t2, 32);
> tcg_gen_trunc_i64_tl(t1, t2);
> tcg_temp_free_i64(t2);
> - tcg_gen_ext32s_tl(cpu_LO[0], t0);
> - tcg_gen_ext32s_tl(cpu_HI[0], t1);
> + tcg_gen_ext32s_tl(cpu_LO[acc], t0);
> + tcg_gen_ext32s_tl(cpu_HI[acc], t1);
> }
> opn = "multu";
> break;
> @@ -2150,19 +2201,20 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
> {
> TCGv_i64 t2 = tcg_temp_new_i64();
> TCGv_i64 t3 = tcg_temp_new_i64();
> + acc = ((ctx->opcode) >> 11) & 0x03;
>
> tcg_gen_ext_tl_i64(t2, t0);
> tcg_gen_ext_tl_i64(t3, t1);
> tcg_gen_mul_i64(t2, t2, t3);
> - tcg_gen_concat_tl_i64(t3, cpu_LO[0], cpu_HI[0]);
> + tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
> tcg_gen_add_i64(t2, t2, t3);
> tcg_temp_free_i64(t3);
> tcg_gen_trunc_i64_tl(t0, t2);
> tcg_gen_shri_i64(t2, t2, 32);
> tcg_gen_trunc_i64_tl(t1, t2);
> tcg_temp_free_i64(t2);
> - tcg_gen_ext32s_tl(cpu_LO[0], t0);
> - tcg_gen_ext32s_tl(cpu_HI[0], t1);
> + tcg_gen_ext32s_tl(cpu_LO[acc], t0);
> + tcg_gen_ext32s_tl(cpu_HI[acc], t1);
> }
> opn = "madd";
> break;
> @@ -2170,21 +2222,22 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
> {
> TCGv_i64 t2 = tcg_temp_new_i64();
> TCGv_i64 t3 = tcg_temp_new_i64();
> + acc = ((ctx->opcode) >> 11) & 0x03;
>
> tcg_gen_ext32u_tl(t0, t0);
> tcg_gen_ext32u_tl(t1, t1);
> tcg_gen_extu_tl_i64(t2, t0);
> tcg_gen_extu_tl_i64(t3, t1);
> tcg_gen_mul_i64(t2, t2, t3);
> - tcg_gen_concat_tl_i64(t3, cpu_LO[0], cpu_HI[0]);
> + tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
> tcg_gen_add_i64(t2, t2, t3);
> tcg_temp_free_i64(t3);
> tcg_gen_trunc_i64_tl(t0, t2);
> tcg_gen_shri_i64(t2, t2, 32);
> tcg_gen_trunc_i64_tl(t1, t2);
> tcg_temp_free_i64(t2);
> - tcg_gen_ext32s_tl(cpu_LO[0], t0);
> - tcg_gen_ext32s_tl(cpu_HI[0], t1);
> + tcg_gen_ext32s_tl(cpu_LO[acc], t0);
> + tcg_gen_ext32s_tl(cpu_HI[acc], t1);
> }
> opn = "maddu";
> break;
> @@ -2192,19 +2245,20 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
> {
> TCGv_i64 t2 = tcg_temp_new_i64();
> TCGv_i64 t3 = tcg_temp_new_i64();
> + acc = ((ctx->opcode) >> 11) & 0x03;
>
> tcg_gen_ext_tl_i64(t2, t0);
> tcg_gen_ext_tl_i64(t3, t1);
> tcg_gen_mul_i64(t2, t2, t3);
> - tcg_gen_concat_tl_i64(t3, cpu_LO[0], cpu_HI[0]);
> + tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
> tcg_gen_sub_i64(t2, t3, t2);
> tcg_temp_free_i64(t3);
> tcg_gen_trunc_i64_tl(t0, t2);
> tcg_gen_shri_i64(t2, t2, 32);
> tcg_gen_trunc_i64_tl(t1, t2);
> tcg_temp_free_i64(t2);
> - tcg_gen_ext32s_tl(cpu_LO[0], t0);
> - tcg_gen_ext32s_tl(cpu_HI[0], t1);
> + tcg_gen_ext32s_tl(cpu_LO[acc], t0);
> + tcg_gen_ext32s_tl(cpu_HI[acc], t1);
> }
> opn = "msub";
> break;
> @@ -2212,21 +2266,22 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
> {
> TCGv_i64 t2 = tcg_temp_new_i64();
> TCGv_i64 t3 = tcg_temp_new_i64();
> + acc = ((ctx->opcode) >> 11) & 0x03;
>
> tcg_gen_ext32u_tl(t0, t0);
> tcg_gen_ext32u_tl(t1, t1);
> tcg_gen_extu_tl_i64(t2, t0);
> tcg_gen_extu_tl_i64(t3, t1);
> tcg_gen_mul_i64(t2, t2, t3);
> - tcg_gen_concat_tl_i64(t3, cpu_LO[0], cpu_HI[0]);
> + tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
> tcg_gen_sub_i64(t2, t3, t2);
> tcg_temp_free_i64(t3);
> tcg_gen_trunc_i64_tl(t0, t2);
> tcg_gen_shri_i64(t2, t2, 32);
> tcg_gen_trunc_i64_tl(t1, t2);
> tcg_temp_free_i64(t2);
> - tcg_gen_ext32s_tl(cpu_LO[0], t0);
> - tcg_gen_ext32s_tl(cpu_HI[0], t1);
> + tcg_gen_ext32s_tl(cpu_LO[acc], t0);
> + tcg_gen_ext32s_tl(cpu_HI[acc], t1);
> }
> opn = "msubu";
> break;
> --
> 1.7.9.5
>
>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
next prev parent reply other threads:[~2012-08-23 13:33 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-08-21 6:53 [Qemu-devel] [PATCH v6 00/13] QEMU MIPS ASE DSP support Jia Liu
2012-08-21 6:53 ` [Qemu-devel] [PATCH v6 01/13] target-mips-ase-dsp: Add internal functions Jia Liu
2012-08-23 13:31 ` Aurelien Jarno
2012-08-21 6:53 ` [Qemu-devel] [PATCH v6 02/13] target-mips-ase-dsp: Use correct acc value to index cpu_HI/cpu_LO rather than using a fix number Jia Liu
2012-08-23 13:33 ` Aurelien Jarno [this message]
2012-08-21 6:53 ` [Qemu-devel] [PATCH v6 03/13] target-mips-ase-dsp: Add branch instructions Jia Liu
2012-08-23 14:18 ` Aurelien Jarno
2012-08-21 6:53 ` [Qemu-devel] [PATCH v6 04/13] target-mips-ase-dsp: Add load instructions Jia Liu
2012-08-23 14:23 ` Aurelien Jarno
2012-08-21 6:53 ` [Qemu-devel] [PATCH v6 05/13] target-mips-ase-dsp: Add arithmetic instructions Jia Liu
2012-08-23 14:28 ` Aurelien Jarno
2012-08-21 6:53 ` [Qemu-devel] [PATCH v6 06/13] target-mips-ase-dsp: Add GPR Based shift instructions Jia Liu
2012-08-21 6:53 ` [Qemu-devel] [PATCH v6 07/13] target-mips-ase-dsp: Add multiply instructions Jia Liu
2012-08-21 6:53 ` [Qemu-devel] [PATCH v6 08/13] target-mips-ase-dsp: Add bit/manipulation instructions Jia Liu
2012-08-23 14:48 ` Aurelien Jarno
2012-08-21 6:53 ` [Qemu-devel] [PATCH v6 09/13] target-mips-ase-dsp: Add compare pick instructions Jia Liu
2012-08-21 6:53 ` [Qemu-devel] [PATCH v6 10/13] target-mips-ase-dsp: Add MIPS ASE DSP Accumulator and DSPControl Access instructions Jia Liu
2012-08-21 6:53 ` [Qemu-devel] [PATCH v6 11/13] target-mips-ase-dsp: Add MIPS[32|64] ASE DSP[R1|R2] generic cpu model Jia Liu
2012-08-21 9:32 ` [Qemu-devel] [PATCH v6 12/13] target-mips-ase-dsp: Add testcases Jia Liu
2012-08-21 9:34 ` [Qemu-devel] [PATCH v6 13/13] target-mips-ase-dsp: Change TODO Jia Liu
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