From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:37016) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TCHGI-0003gd-Lz for qemu-devel@nongnu.org; Thu, 13 Sep 2012 17:47:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TCHGH-0006PL-7K for qemu-devel@nongnu.org; Thu, 13 Sep 2012 17:47:50 -0400 Received: from hall.aurel32.net ([88.191.126.93]:41817) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TCHGH-0006PD-0j for qemu-devel@nongnu.org; Thu, 13 Sep 2012 17:47:49 -0400 Date: Thu, 13 Sep 2012 23:47:42 +0200 From: Aurelien Jarno Message-ID: <20120913214742.GC6791@ohm.aurel32.net> References: <1347557866-7256-1-git-send-email-sw@weilnetz.de> <1347557866-7256-3-git-send-email-sw@weilnetz.de> <20120913212157.GA840@ohm.aurel32.net> <5052507C.7010603@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline In-Reply-To: <5052507C.7010603@twiddle.net> Subject: Re: [Qemu-devel] [PATCH 2/4] tcg/i386: Add shortcuts for registers used in L constraint List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson Cc: Blue Swirl , Peter Maydell , Alexander Graf , qemu-devel@nongnu.org, Stefan Weil On Thu, Sep 13, 2012 at 02:30:36PM -0700, Richard Henderson wrote: > On 09/13/2012 02:21 PM, Aurelien Jarno wrote: > >> > #if TCG_TARGET_REG_BITS == 32 > >> > tcg_out_ld(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP, > >> > (ARRAY_SIZE(tcg_target_callee_save_regs) + 1) * 4); > >> > - tcg_out_ld(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[1], TCG_REG_ESP, > >> > + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_L1, TCG_REG_ESP, > >> > (ARRAY_SIZE(tcg_target_callee_save_regs) + 2) * 4); > >> > #else > >> > - tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); > >> > + tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_L0); > >> > #endif > >> > tcg_out_addi(s, TCG_REG_ESP, -stack_addend); > >> > > >> > /* jmp *tb. */ > >> > - tcg_out_modrm(s, OPC_GRP5, EXT5_JMPN_Ev, tcg_target_call_iarg_regs[1]); > >> > + tcg_out_modrm(s, OPC_GRP5, EXT5_JMPN_Ev, TCG_REG_L1); > > I don't think this is correct here. This has nothing to do with the L > > constraint, it's really refers to the first and seconds argument passed > > to the prologue. > > > > In the 32-bit case, our use of TCG_REG_L1 really is just a temporary. > We loaded it from the stack just above there. Yeah, I missed this one. This should probably be replaced directly by the name of the register. > For the 64-bit case you're right. But that's exactly how we set up > the Ln macros, so I think that's ok. > Then we should change the name and especially the comment above it. They are just #define for the first argument registers, and not related to the 'L' constraint. -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurelien@aurel32.net http://www.aurel32.net