From: Ralf Baechle <ralf@linux-mips.org>
To: Gabor Juhos <juhosg@openwrt.org>
Cc: linux-mips@linux-mips.org, stable@vger.kernel.org
Subject: Re: [PATCH] MIPS: ath79: fix CPU/DDR frequency calculation for SRIF PLLs
Date: Sun, 23 Sep 2012 19:48:51 +0200 [thread overview]
Message-ID: <20120923174851.GG13842@linux-mips.org> (raw)
In-Reply-To: <1347105741-23091-1-git-send-email-juhosg@openwrt.org>
On Sat, Sep 08, 2012 at 02:02:21PM +0200, Gabor Juhos wrote:
Applied but I had to fix a conflict:
@@ -65,6 +65,8 @@
#define AR934X_WMAC_SIZE 0x20000
#define AR934X_EHCI_BASE 0x1b000000
#define AR934X_EHCI_SIZE 0x200
+#define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
+#define AR934X_SRIF_SIZE 0x1000
/*
* DDR_CTRL block
The EHCI lines don't exist yet. Seems harmless though.
Ralf
next prev parent reply other threads:[~2012-09-23 17:48 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-09-08 12:02 [PATCH] MIPS: ath79: fix CPU/DDR frequency calculation for SRIF PLLs Gabor Juhos
2012-09-08 12:02 ` Gabor Juhos
2012-09-23 17:48 ` Ralf Baechle [this message]
2012-09-24 7:26 ` Gabor Juhos
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