From: Marek Vasut <marex@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] Performance of the ARM's PL310 L2 cache.
Date: Sun, 23 Sep 2012 22:12:04 +0200 [thread overview]
Message-ID: <201209232212.04690.marex@denx.de> (raw)
In-Reply-To: <20120817190947.GE3255@bill-the-cat>
Dear Tom Rini,
> On Fri, Aug 17, 2012 at 05:49:53PM +0200, Lukasz Majewski wrote:
> > Hi Aneesh,
> >
> > I've enabled the L2 cache for Trats board. Please find results from
> > performance tests.
> > The test function as well as my way for enabling L2 are attached to
> > this e-mail.
>
> [snip]
>
> > Have you had similar results with OMAP?
> > Do you do more configuration when enabling the L2 at OMAP?
>
> At least on some parts, it's similar here. The normal sequence of
> operations is loading a relatively small payload (kernel, maybe device
> tree) from storage and then booting it (which turns off L2 anyways).
> This is why I was willing to disable DCACHE as a USB workaround, the
> common use-case doesn't see a great deal of help from dcache being on.
I saw some pretty significant perf. boost with L1, I was planning to check L2 on
mx6q, but I'm not sure if it's worth it anymore.
Best regards,
Marek Vasut
next prev parent reply other threads:[~2012-09-23 20:12 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-08-17 15:49 [U-Boot] Performance of the ARM's PL310 L2 cache Lukasz Majewski
2012-08-17 19:09 ` Tom Rini
2012-09-23 20:12 ` Marek Vasut [this message]
2012-10-01 8:23 ` Lukasz Majewski
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