From mboxrd@z Thu Jan  1 00:00:00 1970
From: Jesse Barnes <jbarnes@virtuousgeek.org>
Subject: Re: [PATCH 3/9] drm/i915: add a HSW scratch location
 for flush commands
Date: Tue, 25 Sep 2012 04:08:09 -0700
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To: Daniel Vetter <daniel@ffwll.ch>
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On Tue, 25 Sep 2012 10:54:00 +0200
Daniel Vetter <daniel@ffwll.ch> wrote:

> On Wed, Sep 19, 2012 at 01:28:57PM -0700, Jesse Barnes wrote:
> > Some commands and workarounds require stores to occur to function
> > correctly, so add some scratch space to the HWS page to accommodate
> > them.
> > 
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> > ---
> >  drivers/gpu/drm/i915/intel_ringbuffer.h |    1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> > index 2ea7a31..ef85742 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> > @@ -181,6 +181,7 @@ intel_read_status_page(struct intel_ring_buffer *ring,
> >   * The area from dword 0x20 to 0x3ff is available for driver usage.
> >   */
> >  #define I915_GEM_HWS_INDEX		0x20
> > +#define I915_GEM_SCRATCH_INDEX		0x28 /* Some commands need a scratch store */
> 
> Any specific reason for using an index divisible by 8? Afaik this is an
> index, and the hw multiplies by 4 on it's own. So looks a bit puzzling
> when reading (since iirc only 0x21 is used anywhere else, in some dri1
> stuff).

I got scared when I saw something about qword alignment in the docs.

-- 
Jesse Barnes, Intel Open Source Technology Center