From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 6/9] drm/i915: Add eDP support for Valleyview Date: Wed, 26 Sep 2012 16:31:46 +0200 Message-ID: <20120926143146.GJ1980@bremse> References: <1348666658-31345-1-git-send-email-vijay.a.purushothaman@intel.com> <1348666658-31345-7-git-send-email-vijay.a.purushothaman@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-la0-f49.google.com (mail-la0-f49.google.com [209.85.215.49]) by gabe.freedesktop.org (Postfix) with ESMTP id 964D59E7A8 for ; Wed, 26 Sep 2012 07:31:52 -0700 (PDT) Received: by lagz14 with SMTP id z14so70860lag.36 for ; Wed, 26 Sep 2012 07:31:51 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1348666658-31345-7-git-send-email-vijay.a.purushothaman@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Vijay Purushothaman Cc: Intel Graphics List-Id: intel-gfx@lists.freedesktop.org On Wed, Sep 26, 2012 at 07:07:35PM +0530, Vijay Purushothaman wrote: > Eventhough Valleyview display block is derived from Cantiga, VLV > supports eDP. So, added eDP checks in i9xx_crtc_mode_set path. > > v2: use different DPIO_DIVISOR values for VGA, DP and eDP > v3: fix DPIO value calculation to use same values for all display > interfaces > > Signed-off-by: Gajanan Bhat > Signed-off-by: Vijay Purushothaman > Signed-off-by: Ben Widawsky > --- > drivers/gpu/drm/i915/intel_display.c | 6 ++++++ > drivers/gpu/drm/i915/intel_dp.c | 13 ++++++++----- > 2 files changed, 14 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index a8a81d1..aee6151 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -4405,6 +4405,12 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, > } > } > > + if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) { > + pipeconf |= PIPECONF_BPP_6 | > + PIPECONF_ENABLE | > + I965_PIPECONF_ACTIVE; > + } No. Jani Nikula and me just figured out that we have a giant mess with 6bpc dithering on DP outputs, but unconditionally enabling 6bpc on vlv eDP only papers over issues. > + > DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); > drm_mode_debug_printmodeline(mode); > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index c111c3f..af57027 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -885,7 +885,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, > > /* Split out the IBX/CPU vs CPT settings */ > > - if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) { > + if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { > if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) > intel_dp->DP |= DP_SYNC_HS_HIGH; > if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) > @@ -1474,7 +1474,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) > { > struct drm_device *dev = intel_dp->base.base.dev; > > - if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) { > + if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) { > switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { > case DP_TRAIN_VOLTAGE_SWING_400: > return DP_TRAIN_PRE_EMPHASIS_6; > @@ -1773,7 +1773,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp) > uint32_t signal_levels; > > > - if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) { > + if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) { > signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]); > DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels; > } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) { > @@ -1859,7 +1859,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp) > break; > } > > - if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) { > + if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) { > signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]); > DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels; > } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) { > @@ -2471,7 +2471,10 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port) > if (intel_dpd_is_edp(dev)) > intel_dp->is_pch_edp = true; > > - if (output_reg == DP_A || is_pch_edp(intel_dp)) { > + if (IS_VALLEYVIEW(dev) && output_reg == DP_C) { > + type = DRM_MODE_CONNECTOR_eDP; > + intel_encoder->type = INTEL_OUTPUT_EDP; You need to be a notch more careful, since since commit cb0953d734348e8862d6d7edc666cfb3bf6d8fae Author: Adam Jackson Date: Fri Jul 16 14:46:29 2010 -0400 drm/i915: Initialize LVDS and eDP outputs before anything else We initialize built-in panels before external outputs. Hence you need to adjust intel_setup_outputs for vlv eDP, too, so that the eDP output comes first. A bit a mess, I know. Cheers, Daniel > + } else if (output_reg == DP_A || is_pch_edp(intel_dp)) { > type = DRM_MODE_CONNECTOR_eDP; > intel_encoder->type = INTEL_OUTPUT_EDP; > } else { > -- > 1.7.9.5 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch