From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 10/12] drm/i915: TLB invalidation with MI_FLUSH_SW requires a post-sync op Date: Thu, 4 Oct 2012 10:32:13 +0200 Message-ID: <20121004083213.GB5661@phenom.ffwll.local> References: <1349217826-2538-1-git-send-email-jbarnes@virtuousgeek.org> <1349217826-2538-11-git-send-email-jbarnes@virtuousgeek.org> <20121002171453.3a201ac1@bwidawsk.net> <20121003072020.GB5329@phenom.ffwll.local> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-we0-f177.google.com (mail-we0-f177.google.com [74.125.82.177]) by gabe.freedesktop.org (Postfix) with ESMTP id B687B9E96B for ; Thu, 4 Oct 2012 01:31:19 -0700 (PDT) Received: by mail-we0-f177.google.com with SMTP id u50so168939wey.36 for ; Thu, 04 Oct 2012 01:31:19 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20121003072020.GB5329@phenom.ffwll.local> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Ben Widawsky Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Wed, Oct 03, 2012 at 09:20:20AM +0200, Daniel Vetter wrote: > On Tue, Oct 02, 2012 at 05:14:53PM -0700, Ben Widawsky wrote: > > s/MI_FLUSH_SW/MI_FLUSH_DW/ > > Applied, with spelling fixed. Thanks for patch&review. This hard-hangs my snb here when X starts (so probably on the very first batch). Impressive! I've dropped this one from -fixes. And since no one piped up that the other w/a patches fix anything, I've moved those two I've merged already to dinq. Totally unrelated, I think I'll instate harsher rules for w/a patches: 1. w/a patches only go in through -fixes if they indeed fix an issue we (or a bug reporter) can reproduce. 2. w/a patches need testcases, too. Either a register check added to i-g-t or if it's a runtime thing, a runtime assert at a nice place (where feasible, ofc). 3. I'll randomly stall patches to bring 2. up to par for existing workarounds. Cheers, Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch