Re: How to do fast accesses to LAPIC TPR under kvm?

[Gleb Natapov <gleb@redhat.com>]

On Thu, Oct 18, 2012 at 09:43:46AM +0200, Stefan Fritsch wrote:
> >Everything that unconditionally traps, and so do CR8 accesses, does not
> >help.
> 
> I was hoping that CR8 access would not trap unconditionally. The AMD
> Programmer's Manual Vol. 2, section 15.21.2 seems to imply that
> there is a mode where this is not the case:
> 
> <quote>
> SVM provides a virtual TPR register, V_TPR, for use by the guest;
> its value is loaded from the VMCB by VMRUN and written back to the
> VMCB by #VMEXIT. The APIC's TPR always controls the task priority
> for physical interrupts, and the V_TPR always controls virtual
> interrupts.
> 
> While running a guest with V_INTR_MASKING cleared to 0:
> * Writes to CR8 affect both the APIC's TPR and the V_TPR register
> * Reads from CR8 operate as they would without SVM
> 
> While running a guest with V_INTR_MASKING set to 1:
> * Writes to CR8 affect only the V_TPR register
> * Reads from CR8 return V_TPR.
> </quote>
> 
> Is V_INTR_MASKING == 1 not used in kvm? Is it not usable at all for
> some reason? Or have I misunderstood the description?
> 
You misunderstood the description. V_INTR_MASKING=1 means that CR8 writes
are not propagated to real HW APIC.

But KVM does not trap access to CR8 unconditionally. It enables CR8
intercept only when there is pending interrupt in IRR that cannot be
immediately delivered due to current TPR value. This should eliminate 99%
of CR8 intercepts.

--
			Gleb.