From mboxrd@z Thu Jan  1 00:00:00 1970
From: Jesse Barnes <jbarnes@virtuousgeek.org>
Subject: Re: [PATCH 4/5] drm/i915/dp: compute the pch dp aux
 divider from the rawclk
Date: Mon, 22 Oct 2012 15:08:11 -0700
Message-ID: <20121022150811.5d2ba59d@jbarnes-desktop>
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To: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Intel Graphics Development <intel-gfx@lists.freedesktop.org>
List-Id: intel-gfx@lists.freedesktop.org

On Sat, 20 Oct 2012 20:57:44 +0200
Daniel Vetter <daniel.vetter@ffwll.ch> wrote:

> Otherwise dp aux won't work on some hsw platforms, since they use a
> different rawclk than the 125MHz clock used thus far.
> 
> To absolutely not change anything, round up: That way we get the old
> 63 divider for the default 125MHz clock.
> 
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index b35d5bd..971c4e4 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -372,7 +372,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
>  		else
>  			aux_clock_divider = 225; /* eDP input clock at 450Mhz */
>  	} else if (HAS_PCH_SPLIT(dev))
> -		aux_clock_divider = 63; /* IRL input clock fixed at 125Mhz */
> +		aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
>  	else
>  		aux_clock_divider = intel_hrawclk(dev) / 2;
>  

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

-- 
Jesse Barnes, Intel Open Source Technology Center