diff for duplicates of <20121023071419.222c46d3@skate>

diff --git a/a/1.txt b/N1/1.txt
index 3f67dc3..969c399 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -8,7 +8,7 @@ On Mon, 22 Oct 2012 23:11:02 +0200, Gregory CLEMENT wrote:
 > 
 > I should have added an explanation in the commit log. I will do it for V2.
 
-Just to expand on Gr?gory's comment: there is per-CPU banking for the
+Just to expand on Grégory's comment: there is per-CPU banking for the
 interrupt controller registers. At 0x21070, you have "virtual"
 registers that automatically map to the interrupt controller registers
 of the current CPU. At 0x21870, you have the interrupt controllers
@@ -31,3 +31,8 @@ Thomas Petazzoni, Free Electrons
 Kernel, drivers, real-time and embedded Linux
 development, consulting, training and support.
 http://free-electrons.com
+
+_______________________________________________
+linux-arm-kernel mailing list
+linux-arm-kernel@lists.infradead.org
+http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
diff --git a/a/content_digest b/N1/content_digest
index a1c5b78..ab24575 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -4,10 +4,34 @@
  "ref\050859976.6080601@free-electrons.com\0"
  "ref\020121022200708.GO21046@lunn.ch\0"
  "ref\05085B666.1040500@free-electrons.com\0"
- "From\0thomas.petazzoni@free-electrons.com (Thomas Petazzoni)\0"
- "Subject\0[PATCH 3/5] arm: mvebu: Added IPI support via doorbells\0"
+ "From\0Thomas Petazzoni <thomas.petazzoni@free-electrons.com>\0"
+ "Subject\0Re: [PATCH 3/5] arm: mvebu: Added IPI support via doorbells\0"
  "Date\0Tue, 23 Oct 2012 07:14:19 +0200\0"
- "To\0linux-arm-kernel@lists.infradead.org\0"
+ "To\0Gregory CLEMENT <gregory.clement@free-electrons.com>\0"
+ "Cc\0Lior Amsalem <alior@marvell.com>"
+  Andrew Lunn <andrew@lunn.ch>
+  Ike Pan <ike.pan@canonical.com>
+  Will Deacon <will.deacon@arm.com>
+  Nadav Haklai <nadavh@marvell.com>
+  Ian Molton <ian.molton@codethink.co.uk>
+  David Marlin <dmarlin@redhat.com>
+  Yehuda Yitschak <yehuday@marvell.com>
+  Jani Monoses <jani.monoses@canonical.com>
+  Russell King <linux@arm.linux.org.uk>
+  Tawfik Bayouk <tawfik@marvell.com>
+  Dan Frazier <dann.frazier@canonical.com>
+  Eran Ben-Avi <benavi@marvell.com>
+  Li Li <li.li@canonical.com>
+  Leif Lindholm <leif.lindholm@arm.com>
+  Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+  Jason Cooper <jason@lakedaemon.net>
+  Arnd Bergmann <arnd@arndb.de>
+  Jon Masters <jcm@redhat.com>
+  devicetree-discuss@lists.ozlabs.org
+  Rob Herring <rob.herring@calxeda.com>
+  Ben Dooks <ben-linux@fluff.org>
+  Mike Turquette <mturquette@linaro.org>
+ " linux-arm-kernel@lists.infradead.or\0"
  "\00:1\0"
  "b\0"
  "\n"
@@ -20,7 +44,7 @@
  "> \n"
  "> I should have added an explanation in the commit log. I will do it for V2.\n"
  "\n"
- "Just to expand on Gr?gory's comment: there is per-CPU banking for the\n"
+ "Just to expand on Gr\303\251gory's comment: there is per-CPU banking for the\n"
  "interrupt controller registers. At 0x21070, you have \"virtual\"\n"
  "registers that automatically map to the interrupt controller registers\n"
  "of the current CPU. At 0x21870, you have the interrupt controllers\n"
@@ -42,6 +66,11 @@
  "Thomas Petazzoni, Free Electrons\n"
  "Kernel, drivers, real-time and embedded Linux\n"
  "development, consulting, training and support.\n"
- http://free-electrons.com
+ "http://free-electrons.com\n"
+ "\n"
+ "_______________________________________________\n"
+ "linux-arm-kernel mailing list\n"
+ "linux-arm-kernel@lists.infradead.org\n"
+ http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
 
-1233d73f81511c4b6858fe2cf34d5e23334a6b2bfb0a7f98dcffb5cb6b827765
+55682a45a0bfd52a484303daa1f3ea87e6eefd7898635f6e1739bbd211afa429
