From mboxrd@z Thu Jan 1 00:00:00 1970 From: thomas.petazzoni@free-electrons.com (Thomas Petazzoni) Date: Tue, 23 Oct 2012 07:14:19 +0200 Subject: [PATCH 3/5] arm: mvebu: Added IPI support via doorbells In-Reply-To: <5085B666.1040500@free-electrons.com> References: <1350925368-24243-1-git-send-email-gregory.clement@free-electrons.com> <1350925368-24243-4-git-send-email-gregory.clement@free-electrons.com> <20121022173028.GM21046@lunn.ch> <50859976.6080601@free-electrons.com> <20121022200708.GO21046@lunn.ch> <5085B666.1040500@free-electrons.com> Message-ID: <20121023071419.222c46d3@skate> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Mon, 22 Oct 2012 23:11:02 +0200, Gregory CLEMENT wrote: > The correct explanation is that the offset +21070 is a CPU virtual offset. > That means that depending of the CPU core which will access to this register, > the controller will internally change the offset automagically to point the > correct offset. > > I should have added an explanation in the commit log. I will do it for V2. Just to expand on Gr?gory's comment: there is per-CPU banking for the interrupt controller registers. At 0x21070, you have "virtual" registers that automatically map to the interrupt controller registers of the current CPU. At 0x21870, you have the interrupt controllers registers of CPU0, regardless of which CPU you are running on. Before this patch set, there was no SMP support for Armada 370/XP, so accessing the interrupt controller registers at 0x21870 was OK (accessing them from 0x21070 would have been OK as well). With the introduction of SMP support, accessing them from 0x21870 no longer works, so we switch to the virtual registers at 0x21070. In other words: no it is not a bug fix and it therefore doesn't need to go into 3.7. Best regards, Thomas -- Thomas Petazzoni, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com From mboxrd@z Thu Jan 1 00:00:00 1970 From: Thomas Petazzoni Subject: Re: [PATCH 3/5] arm: mvebu: Added IPI support via doorbells Date: Tue, 23 Oct 2012 07:14:19 +0200 Message-ID: <20121023071419.222c46d3@skate> References: <1350925368-24243-1-git-send-email-gregory.clement@free-electrons.com> <1350925368-24243-4-git-send-email-gregory.clement@free-electrons.com> <20121022173028.GM21046@lunn.ch> <50859976.6080601@free-electrons.com> <20121022200708.GO21046@lunn.ch> <5085B666.1040500@free-electrons.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <5085B666.1040500@free-electrons.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Gregory CLEMENT Cc: Lior Amsalem , Andrew Lunn , Ike Pan , Will Deacon , Nadav Haklai , Ian Molton , David Marlin , Yehuda Yitschak , Jani Monoses , Russell King , Tawfik Bayouk , Dan Frazier , Eran Ben-Avi , Li Li , Leif Lindholm , Sebastian Hesselbarth , Jason Cooper , Arnd Bergmann , Jon Masters , devicetree-discuss@lists.ozlabs.org, Rob Herring , Ben Dooks , Mike Turquette , linux-arm-kernel@lists.infradead.or List-Id: devicetree@vger.kernel.org Ck9uIE1vbiwgMjIgT2N0IDIwMTIgMjM6MTE6MDIgKzAyMDAsIEdyZWdvcnkgQ0xFTUVOVCB3cm90 ZToKCj4gVGhlIGNvcnJlY3QgZXhwbGFuYXRpb24gaXMgdGhhdCB0aGUgb2Zmc2V0ICsyMTA3MCBp cyBhIENQVSB2aXJ0dWFsIG9mZnNldC4KPiBUaGF0IG1lYW5zIHRoYXQgZGVwZW5kaW5nIG9mIHRo ZSBDUFUgY29yZSB3aGljaCB3aWxsIGFjY2VzcyB0byB0aGlzIHJlZ2lzdGVyLAo+IHRoZSBjb250 cm9sbGVyIHdpbGwgaW50ZXJuYWxseSBjaGFuZ2UgdGhlIG9mZnNldCBhdXRvbWFnaWNhbGx5IHRv IHBvaW50IHRoZQo+IGNvcnJlY3Qgb2Zmc2V0Lgo+IAo+IEkgc2hvdWxkIGhhdmUgYWRkZWQgYW4g ZXhwbGFuYXRpb24gaW4gdGhlIGNvbW1pdCBsb2cuIEkgd2lsbCBkbyBpdCBmb3IgVjIuCgpKdXN0 IHRvIGV4cGFuZCBvbiBHcsOpZ29yeSdzIGNvbW1lbnQ6IHRoZXJlIGlzIHBlci1DUFUgYmFua2lu ZyBmb3IgdGhlCmludGVycnVwdCBjb250cm9sbGVyIHJlZ2lzdGVycy4gQXQgMHgyMTA3MCwgeW91 IGhhdmUgInZpcnR1YWwiCnJlZ2lzdGVycyB0aGF0IGF1dG9tYXRpY2FsbHkgbWFwIHRvIHRoZSBp bnRlcnJ1cHQgY29udHJvbGxlciByZWdpc3RlcnMKb2YgdGhlIGN1cnJlbnQgQ1BVLiBBdCAweDIx ODcwLCB5b3UgaGF2ZSB0aGUgaW50ZXJydXB0IGNvbnRyb2xsZXJzCnJlZ2lzdGVycyBvZiBDUFUw LCByZWdhcmRsZXNzIG9mIHdoaWNoIENQVSB5b3UgYXJlIHJ1bm5pbmcgb24uCgpCZWZvcmUgdGhp cyBwYXRjaCBzZXQsIHRoZXJlIHdhcyBubyBTTVAgc3VwcG9ydCBmb3IgQXJtYWRhIDM3MC9YUCwg c28KYWNjZXNzaW5nIHRoZSBpbnRlcnJ1cHQgY29udHJvbGxlciByZWdpc3RlcnMgYXQgMHgyMTg3 MCB3YXMgT0sKKGFjY2Vzc2luZyB0aGVtIGZyb20gMHgyMTA3MCB3b3VsZCBoYXZlIGJlZW4gT0sg YXMgd2VsbCkuIFdpdGggdGhlCmludHJvZHVjdGlvbiBvZiBTTVAgc3VwcG9ydCwgYWNjZXNzaW5n IHRoZW0gZnJvbSAweDIxODcwIG5vIGxvbmdlcgp3b3Jrcywgc28gd2Ugc3dpdGNoIHRvIHRoZSB2 aXJ0dWFsIHJlZ2lzdGVycyBhdCAweDIxMDcwLgoKSW4gb3RoZXIgd29yZHM6IG5vIGl0IGlzIG5v dCBhIGJ1ZyBmaXggYW5kIGl0IHRoZXJlZm9yZSBkb2Vzbid0IG5lZWQgdG8KZ28gaW50byAzLjcu CgpCZXN0IHJlZ2FyZHMsCgpUaG9tYXMKLS0gClRob21hcyBQZXRhenpvbmksIEZyZWUgRWxlY3Ry b25zCktlcm5lbCwgZHJpdmVycywgcmVhbC10aW1lIGFuZCBlbWJlZGRlZCBMaW51eApkZXZlbG9w bWVudCwgY29uc3VsdGluZywgdHJhaW5pbmcgYW5kIHN1cHBvcnQuCmh0dHA6Ly9mcmVlLWVsZWN0 cm9ucy5jb20KCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f CmxpbnV4LWFybS1rZXJuZWwgbWFpbGluZyBsaXN0CmxpbnV4LWFybS1rZXJuZWxAbGlzdHMuaW5m cmFkZWFkLm9yZwpodHRwOi8vbGlzdHMuaW5mcmFkZWFkLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2xp bnV4LWFybS1rZXJuZWwK