From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jesse Barnes Subject: Re: [PATCH 03/10] drm/i915: introduce gtt_pte_t Date: Thu, 25 Oct 2012 13:49:13 -0700 Message-ID: <20121025134913.24ee2f06@jbarnes-desktop> References: <1350956055-3224-1-git-send-email-ben@bwidawsk.net> <1350956055-3224-4-git-send-email-ben@bwidawsk.net> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from oproxy11-pub.bluehost.com (oproxy11-pub.bluehost.com [173.254.64.10]) by gabe.freedesktop.org (Postfix) with SMTP id 56046A0AC5 for ; Thu, 25 Oct 2012 13:49:14 -0700 (PDT) In-Reply-To: <1350956055-3224-4-git-send-email-ben@bwidawsk.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Ben Widawsky Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Mon, 22 Oct 2012 18:34:08 -0700 Ben Widawsky wrote: > This will make the calculations of size easier to read instead of just > assuming uint32_t everywhere. > > Signed-off-by: Ben Widawsky > --- > drivers/gpu/drm/i915/i915_gem_gtt.c | 14 ++++++++------ > 1 file changed, 8 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c > index 2b75028..a769b3c 100644 > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c > @@ -29,13 +29,15 @@ > #include "i915_trace.h" > #include "intel_drv.h" > > +typedef uint32_t gtt_pte_t; > + > /* PPGTT support for Sandybdrige/Gen6 and later */ > static void i915_ppgtt_clear_range(struct i915_hw_ppgtt *ppgtt, > unsigned first_entry, > unsigned num_entries) > { > - uint32_t *pt_vaddr; > - uint32_t scratch_pte; > + gtt_pte_t *pt_vaddr; > + gtt_pte_t scratch_pte; > unsigned act_pd = first_entry / I915_PPGTT_PT_ENTRIES; > unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES; > unsigned last_pte, i; > @@ -120,7 +122,7 @@ int i915_gem_init_aliasing_ppgtt(struct drm_device *dev) > i915_ppgtt_clear_range(ppgtt, 0, > ppgtt->num_pd_entries*I915_PPGTT_PT_ENTRIES); > > - ppgtt->pd_offset = (first_pd_entry_in_global_pt)*sizeof(uint32_t); > + ppgtt->pd_offset = (first_pd_entry_in_global_pt)*sizeof(gtt_pte_t); > > dev_priv->mm.aliasing_ppgtt = ppgtt; > > @@ -170,9 +172,9 @@ void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev) > static void i915_ppgtt_insert_sg_entries(struct i915_hw_ppgtt *ppgtt, > const struct sg_table *pages, > unsigned first_entry, > - uint32_t pte_flags) > + gtt_pte_t pte_flags) > { > - uint32_t *pt_vaddr, pte; > + gtt_pte_t *pt_vaddr, pte; > unsigned act_pd = first_entry / I915_PPGTT_PT_ENTRIES; > unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES; > unsigned i, j, m, segment_len; > @@ -215,7 +217,7 @@ void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, > struct drm_i915_gem_object *obj, > enum i915_cache_level cache_level) > { > - uint32_t pte_flags = GEN6_PTE_VALID; > + gtt_pte_t pte_flags = GEN6_PTE_VALID; > > switch (cache_level) { > case I915_CACHE_LLC_MLC: Reviewed-by: Jesse Barnes -- Jesse Barnes, Intel Open Source Technology Center