From mboxrd@z Thu Jan  1 00:00:00 1970
From: Daniel Vetter <daniel@ffwll.ch>
Subject: Re: [PATCH] drm/i915: Fix HSW power well control state
 read
Date: Tue, 30 Oct 2012 20:37:46 +0100
Message-ID: <20121030193746.GC5755@phenom.ffwll.local>
References: <1351595794-4378-1-git-send-email-zhenyuw@linux.intel.com>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
Return-path: <intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org>
Received: from mail-ea0-f177.google.com (mail-ea0-f177.google.com
	[209.85.215.177])
	by gabe.freedesktop.org (Postfix) with ESMTP id B15E39EB4F
	for <intel-gfx@lists.freedesktop.org>;
	Tue, 30 Oct 2012 12:36:42 -0700 (PDT)
Received: by mail-ea0-f177.google.com with SMTP id n13so261603eaa.36
	for <intel-gfx@lists.freedesktop.org>;
	Tue, 30 Oct 2012 12:36:40 -0700 (PDT)
Content-Disposition: inline
In-Reply-To: <1351595794-4378-1-git-send-email-zhenyuw@linux.intel.com>
List-Unsubscribe: <http://lists.freedesktop.org/mailman/options/intel-gfx>,
	<mailto:intel-gfx-request@lists.freedesktop.org?subject=unsubscribe>
List-Archive: <http://lists.freedesktop.org/archives/intel-gfx>
List-Post: <mailto:intel-gfx@lists.freedesktop.org>
List-Help: <mailto:intel-gfx-request@lists.freedesktop.org?subject=help>
List-Subscribe: <http://lists.freedesktop.org/mailman/listinfo/intel-gfx>,
	<mailto:intel-gfx-request@lists.freedesktop.org?subject=subscribe>
Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org
Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org
To: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
List-Id: intel-gfx@lists.freedesktop.org

On Tue, Oct 30, 2012 at 07:16:34PM +0800, Zhenyu Wang wrote:
> Fix power well control state by reading real register offset.
> 
> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Queued for -next, thanks for the patch.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch