Re: [PATCH] TTY: serial 8250: Support MCR CLK_SEL bit.

[Alan Cox <alan@lxorguk.ukuu.org.uk>]

> This chip is a DUART but the clksel bit, although present for
> both channels, (in MCR bit 7) is actually shared (as is the external
> CLKSEL pin). Hence if the kernel determines whether to enable
> /4 or /1 based on the requested baud rate for one channel it
> may break the baud rate for the other channel.

Gak.

> As a general question how should this type of dependency between
> ports due to them being part of the same chip be handled?

It sounds to me an even bigger reason for having the kernel 8250 termios
code have a ->clock_select() method but you'd need some way to find the
pair of the device. Ok thats uglier. Can you at least define the DT as
setting the *initial* divisor. That way we can later fix the kernel to be
smart about clocks without breaking any assumption about what the DT
entry means.

> So I've just refactored the existing code to share setting this bit -
> this shouldn't change the existing behaviour.
> 
> Maybe I should have done this as a seperate patch to make it clearer.

Got it - and yes please make that a separate patch.
 
> If UART_CAP_EFR is not set but UART_CAP_SLEEP or UART_CAP_CLKSEL is
> set is assumed that it is not necessary to enable access via the EFR 
> (whether
> that is a valid combination for any existing UART is another question).

Probably not.

Alan