From mboxrd@z Thu Jan  1 00:00:00 1970
From: Thierry Reding <thierry.reding-RM9K5IK7kjKj5M59NBduVrNAH6kLmebB@public.gmane.org>
Subject: Re: [PATCH 1/6] video: tegra: Add nvhost driver
Date: Fri, 23 Nov 2012 16:29:27 +0100
Message-ID: <20121123152926.GA20046@avionic-0098.adnet.avionic-design.de>
References: <1353586614-7308-1-git-send-email-tbergstrom@nvidia.com>
 <1353586614-7308-2-git-send-email-tbergstrom@nvidia.com>
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Sender: linux-tegra-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
To: Terje Bergstrom <tbergstrom-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Arto Merilainen <amerilainen-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
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On Thu, Nov 22, 2012 at 02:16:49PM +0200, Terje Bergstrom wrote:
[...]
> diff --git a/drivers/video/tegra/host/host1x/hw_host1x01_channel.h b/drivers/video/tegra/host/host1x/hw_host1x01_channel.h
> new file mode 100644
> index 0000000..ca2f9a0
> --- /dev/null
> +++ b/drivers/video/tegra/host/host1x/hw_host1x01_channel.h
> @@ -0,0 +1,182 @@
> +/*
> + * drivers/video/tegra/host/host1x/hw_host1x_channel_host1x.h
> + *
> + * Copyright (c) 2012, NVIDIA Corporation.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
> + *
> + */
> +
> + /*
> +  * Function naming determines intended use:
> +  *
> +  *     <x>_r(void) : Returns the offset for register <x>.
> +  *
> +  *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
> +  *
> +  *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
> +  *
> +  *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
> +  *         and masked to place it at field <y> of register <x>.  This value
> +  *         can be |'d with others to produce a full register value for
> +  *         register <x>.
> +  *
> +  *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
> +  *         value can be ~'d and then &'d to clear the value of field <y> for
> +  *         register <x>.
> +  *
> +  *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
> +  *         to place it at field <y> of register <x>.  This value can be |'d
> +  *         with others to produce a full register value for <x>.
> +  *
> +  *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
> +  *         <x> value 'r' after being shifted to place its LSB at bit 0.
> +  *         This value is suitable for direct comparison with other unshifted
> +  *         values appropriate for use in field <y> of register <x>.
> +  *
> +  *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
> +  *         field <y> of register <x>.  This value is suitable for direct
> +  *         comparison with unshifted values appropriate for use in field <y>
> +  *         of register <x>.
> +  */
> +
> +#ifndef __hw_host1x_channel_host1x_h__
> +#define __hw_host1x_channel_host1x_h__
> +/*This file is autogenerated.  Do not edit. */
> +
> +static inline u32 host1x_channel_fifostat_r(void)
> +{
> +	return 0x0;
> +}
> +static inline u32 host1x_channel_fifostat_cfempty_s(void)
> +{
> +	return 1;
> +}
> +static inline u32 host1x_channel_fifostat_cfempty_f(u32 v)
> +{
> +	return (v & 0x1) << 10;
> +}
> +static inline u32 host1x_channel_fifostat_cfempty_m(void)
> +{
> +	return 0x1 << 10;
> +}
> +static inline u32 host1x_channel_fifostat_cfempty_v(u32 r)
> +{
> +	return (r >> 10) & 0x1;
> +}
> +static inline u32 host1x_channel_fifostat_cfempty_notempty_v(void)
> +{
> +	return 0;
> +}
> +static inline u32 host1x_channel_fifostat_cfempty_empty_v(void)
> +{
> +	return 1;
> +}
> +static inline u32 host1x_channel_fifostat_outfentries_s(void)
> +{
> +	return 5;
> +}
> +static inline u32 host1x_channel_fifostat_outfentries_f(u32 v)
> +{
> +	return (v & 0x1f) << 24;
> +}
> +static inline u32 host1x_channel_fifostat_outfentries_m(void)
> +{
> +	return 0x1f << 24;
> +}
> +static inline u32 host1x_channel_fifostat_outfentries_v(u32 r)
> +{
> +	return (r >> 24) & 0x1f;
> +}
> +static inline u32 host1x_channel_inddata_r(void)
> +{
> +	return 0xc;
> +}
> +static inline u32 host1x_channel_dmastart_r(void)
> +{
> +	return 0x14;
> +}
> +static inline u32 host1x_channel_dmaput_r(void)
> +{
> +	return 0x18;
> +}
> +static inline u32 host1x_channel_dmaget_r(void)
> +{
> +	return 0x1c;
> +}
> +static inline u32 host1x_channel_dmaend_r(void)
> +{
> +	return 0x20;
> +}
> +static inline u32 host1x_channel_dmactrl_r(void)
> +{
> +	return 0x24;
> +}
> +static inline u32 host1x_channel_dmactrl_dmastop_s(void)
> +{
> +	return 1;
> +}
> +static inline u32 host1x_channel_dmactrl_dmastop_f(u32 v)
> +{
> +	return (v & 0x1) << 0;
> +}
> +static inline u32 host1x_channel_dmactrl_dmastop_m(void)
> +{
> +	return 0x1 << 0;
> +}
> +static inline u32 host1x_channel_dmactrl_dmastop_v(u32 r)
> +{
> +	return (r >> 0) & 0x1;
> +}
> +static inline u32 host1x_channel_dmactrl_dmastop_run_v(void)
> +{
> +	return 0;
> +}
> +static inline u32 host1x_channel_dmactrl_dmastop_stop_v(void)
> +{
> +	return 1;
> +}
> +static inline u32 host1x_channel_dmactrl_dmagetrst_s(void)
> +{
> +	return 1;
> +}
> +static inline u32 host1x_channel_dmactrl_dmagetrst_f(u32 v)
> +{
> +	return (v & 0x1) << 1;
> +}
> +static inline u32 host1x_channel_dmactrl_dmagetrst_m(void)
> +{
> +	return 0x1 << 1;
> +}
> +static inline u32 host1x_channel_dmactrl_dmagetrst_v(u32 r)
> +{
> +	return (r >> 1) & 0x1;
> +}
> +static inline u32 host1x_channel_dmactrl_dmainitget_s(void)
> +{
> +	return 1;
> +}
> +static inline u32 host1x_channel_dmactrl_dmainitget_f(u32 v)
> +{
> +	return (v & 0x1) << 2;
> +}
> +static inline u32 host1x_channel_dmactrl_dmainitget_m(void)
> +{
> +	return 0x1 << 2;
> +}
> +static inline u32 host1x_channel_dmactrl_dmainitget_v(u32 r)
> +{
> +	return (r >> 2) & 0x1;
> +}
> +
> +#endif /* __hw_host1x_channel_host1x_h__ */
> diff --git a/drivers/video/tegra/host/host1x/hw_host1x01_sync.h b/drivers/video/tegra/host/host1x/hw_host1x01_sync.h
> new file mode 100644
> index 0000000..67f0cbf
> --- /dev/null
> +++ b/drivers/video/tegra/host/host1x/hw_host1x01_sync.h
> @@ -0,0 +1,398 @@
> +/*
> + * drivers/video/tegra/host/host1x/hw_host1x_sync_host1x.h
> + *
> + * Copyright (c) 2012, NVIDIA Corporation.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
> + *
> + */
> +
> + /*
> +  * Function naming determines intended use:
> +  *
> +  *     <x>_r(void) : Returns the offset for register <x>.
> +  *
> +  *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
> +  *
> +  *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
> +  *
> +  *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
> +  *         and masked to place it at field <y> of register <x>.  This value
> +  *         can be |'d with others to produce a full register value for
> +  *         register <x>.
> +  *
> +  *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
> +  *         value can be ~'d and then &'d to clear the value of field <y> for
> +  *         register <x>.
> +  *
> +  *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
> +  *         to place it at field <y> of register <x>.  This value can be |'d
> +  *         with others to produce a full register value for <x>.
> +  *
> +  *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
> +  *         <x> value 'r' after being shifted to place its LSB at bit 0.
> +  *         This value is suitable for direct comparison with other unshifted
> +  *         values appropriate for use in field <y> of register <x>.
> +  *
> +  *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
> +  *         field <y> of register <x>.  This value is suitable for direct
> +  *         comparison with unshifted values appropriate for use in field <y>
> +  *         of register <x>.
> +  */
> +
> +#ifndef __hw_host1x_sync_host1x_h__
> +#define __hw_host1x_sync_host1x_h__
> +/*This file is autogenerated.  Do not edit. */
> +
> +static inline u32 host1x_sync_intmask_r(void)
> +{
> +	return 0x4;
> +}
> +static inline u32 host1x_sync_intc0mask_r(void)
> +{
> +	return 0x8;
> +}
> +static inline u32 host1x_sync_hintstatus_r(void)
> +{
> +	return 0x20;
> +}
> +static inline u32 host1x_sync_hintmask_r(void)
> +{
> +	return 0x24;
> +}
> +static inline u32 host1x_sync_hintstatus_ext_r(void)
> +{
> +	return 0x28;
> +}
> +static inline u32 host1x_sync_hintstatus_ext_ip_read_int_s(void)
> +{
> +	return 1;
> +}
> +static inline u32 host1x_sync_hintstatus_ext_ip_read_int_f(u32 v)
> +{
> +	return (v & 0x1) << 30;
> +}
> +static inline u32 host1x_sync_hintstatus_ext_ip_read_int_m(void)
> +{
> +	return 0x1 << 30;
> +}
> +static inline u32 host1x_sync_hintstatus_ext_ip_read_int_v(u32 r)
> +{
> +	return (r >> 30) & 0x1;
> +}
> +static inline u32 host1x_sync_hintstatus_ext_ip_write_int_s(void)
> +{
> +	return 1;
> +}
> +static inline u32 host1x_sync_hintstatus_ext_ip_write_int_f(u32 v)
> +{
> +	return (v & 0x1) << 31;
> +}
> +static inline u32 host1x_sync_hintstatus_ext_ip_write_int_m(void)
> +{
> +	return 0x1 << 31;
> +}
> +static inline u32 host1x_sync_hintstatus_ext_ip_write_int_v(u32 r)
> +{
> +	return (r >> 31) & 0x1;
> +}
> +static inline u32 host1x_sync_hintmask_ext_r(void)
> +{
> +	return 0x2c;
> +}
> +static inline u32 host1x_sync_syncpt_thresh_cpu0_int_status_r(void)
> +{
> +	return 0x40;
> +}
> +static inline u32 host1x_sync_syncpt_thresh_cpu1_int_status_r(void)
> +{
> +	return 0x48;
> +}
> +static inline u32 host1x_sync_syncpt_thresh_int_disable_r(void)
> +{
> +	return 0x60;
> +}
> +static inline u32 host1x_sync_syncpt_thresh_int_enable_cpu0_r(void)
> +{
> +	return 0x68;
> +}
> +static inline u32 host1x_sync_cf0_setup_r(void)
> +{
> +	return 0x80;
> +}
> +static inline u32 host1x_sync_cf0_setup_cf0_base_s(void)
> +{
> +	return 9;
> +}
> +static inline u32 host1x_sync_cf0_setup_cf0_base_f(u32 v)
> +{
> +	return (v & 0x1ff) << 0;
> +}
> +static inline u32 host1x_sync_cf0_setup_cf0_base_m(void)
> +{
> +	return 0x1ff << 0;
> +}
> +static inline u32 host1x_sync_cf0_setup_cf0_base_v(u32 r)
> +{
> +	return (r >> 0) & 0x1ff;
> +}
> +static inline u32 host1x_sync_cf0_setup_cf0_limit_s(void)
> +{
> +	return 9;
> +}
> +static inline u32 host1x_sync_cf0_setup_cf0_limit_f(u32 v)
> +{
> +	return (v & 0x1ff) << 16;
> +}
> +static inline u32 host1x_sync_cf0_setup_cf0_limit_m(void)
> +{
> +	return 0x1ff << 16;
> +}
> +static inline u32 host1x_sync_cf0_setup_cf0_limit_v(u32 r)
> +{
> +	return (r >> 16) & 0x1ff;
> +}
> +static inline u32 host1x_sync_cmdproc_stop_r(void)
> +{
> +	return 0xac;
> +}
> +static inline u32 host1x_sync_ch_teardown_r(void)
> +{
> +	return 0xb0;
> +}
> +static inline u32 host1x_sync_usec_clk_r(void)
> +{
> +	return 0x1a4;
> +}
> +static inline u32 host1x_sync_ctxsw_timeout_cfg_r(void)
> +{
> +	return 0x1a8;
> +}
> +static inline u32 host1x_sync_ip_busy_timeout_r(void)
> +{
> +	return 0x1bc;
> +}
> +static inline u32 host1x_sync_ip_read_timeout_addr_r(void)
> +{
> +	return 0x1c0;
> +}
> +static inline u32 host1x_sync_ip_write_timeout_addr_r(void)
> +{
> +	return 0x1c4;
> +}
> +static inline u32 host1x_sync_mlock_0_r(void)
> +{
> +	return 0x2c0;
> +}
> +static inline u32 host1x_sync_mlock_owner_0_r(void)
> +{
> +	return 0x340;
> +}
> +static inline u32 host1x_sync_mlock_owner_0_mlock_owner_chid_0_s(void)
> +{
> +	return 4;
> +}
> +static inline u32 host1x_sync_mlock_owner_0_mlock_owner_chid_0_f(u32 v)
> +{
> +	return (v & 0xf) << 8;
> +}
> +static inline u32 host1x_sync_mlock_owner_0_mlock_owner_chid_0_m(void)
> +{
> +	return 0xf << 8;
> +}
> +static inline u32 host1x_sync_mlock_owner_0_mlock_owner_chid_0_v(u32 r)
> +{
> +	return (r >> 8) & 0xf;
> +}
> +static inline u32 host1x_sync_mlock_owner_0_mlock_cpu_owns_0_s(void)
> +{
> +	return 1;
> +}
> +static inline u32 host1x_sync_mlock_owner_0_mlock_cpu_owns_0_f(u32 v)
> +{
> +	return (v & 0x1) << 1;
> +}
> +static inline u32 host1x_sync_mlock_owner_0_mlock_cpu_owns_0_m(void)
> +{
> +	return 0x1 << 1;
> +}
> +static inline u32 host1x_sync_mlock_owner_0_mlock_cpu_owns_0_v(u32 r)
> +{
> +	return (r >> 1) & 0x1;
> +}
> +static inline u32 host1x_sync_mlock_owner_0_mlock_ch_owns_0_s(void)
> +{
> +	return 1;
> +}
> +static inline u32 host1x_sync_mlock_owner_0_mlock_ch_owns_0_f(u32 v)
> +{
> +	return (v & 0x1) << 0;
> +}
> +static inline u32 host1x_sync_mlock_owner_0_mlock_ch_owns_0_m(void)
> +{
> +	return 0x1 << 0;
> +}
> +static inline u32 host1x_sync_mlock_owner_0_mlock_ch_owns_0_v(u32 r)
> +{
> +	return (r >> 0) & 0x1;
> +}
> +static inline u32 host1x_sync_syncpt_0_r(void)
> +{
> +	return 0x400;
> +}
> +static inline u32 host1x_sync_syncpt_int_thresh_0_r(void)
> +{
> +	return 0x500;
> +}
> +static inline u32 host1x_sync_syncpt_base_0_r(void)
> +{
> +	return 0x600;
> +}
> +static inline u32 host1x_sync_syncpt_cpu_incr_r(void)
> +{
> +	return 0x700;
> +}
> +static inline u32 host1x_sync_cbread0_r(void)
> +{
> +	return 0x720;
> +}
> +static inline u32 host1x_sync_cfpeek_ctrl_r(void)
> +{
> +	return 0x74c;
> +}
> +static inline u32 host1x_sync_cfpeek_ctrl_cfpeek_addr_s(void)
> +{
> +	return 9;
> +}
> +static inline u32 host1x_sync_cfpeek_ctrl_cfpeek_addr_f(u32 v)
> +{
> +	return (v & 0x1ff) << 0;
> +}
> +static inline u32 host1x_sync_cfpeek_ctrl_cfpeek_addr_m(void)
> +{
> +	return 0x1ff << 0;
> +}
> +static inline u32 host1x_sync_cfpeek_ctrl_cfpeek_addr_v(u32 r)
> +{
> +	return (r >> 0) & 0x1ff;
> +}
> +static inline u32 host1x_sync_cfpeek_ctrl_cfpeek_channr_s(void)
> +{
> +	return 3;
> +}
> +static inline u32 host1x_sync_cfpeek_ctrl_cfpeek_channr_f(u32 v)
> +{
> +	return (v & 0x7) << 16;
> +}
> +static inline u32 host1x_sync_cfpeek_ctrl_cfpeek_channr_m(void)
> +{
> +	return 0x7 << 16;
> +}
> +static inline u32 host1x_sync_cfpeek_ctrl_cfpeek_channr_v(u32 r)
> +{
> +	return (r >> 16) & 0x7;
> +}
> +static inline u32 host1x_sync_cfpeek_ctrl_cfpeek_ena_s(void)
> +{
> +	return 1;
> +}
> +static inline u32 host1x_sync_cfpeek_ctrl_cfpeek_ena_f(u32 v)
> +{
> +	return (v & 0x1) << 31;
> +}
> +static inline u32 host1x_sync_cfpeek_ctrl_cfpeek_ena_m(void)
> +{
> +	return 0x1 << 31;
> +}
> +static inline u32 host1x_sync_cfpeek_ctrl_cfpeek_ena_v(u32 r)
> +{
> +	return (r >> 31) & 0x1;
> +}
> +static inline u32 host1x_sync_cfpeek_read_r(void)
> +{
> +	return 0x750;
> +}
> +static inline u32 host1x_sync_cfpeek_ptrs_r(void)
> +{
> +	return 0x754;
> +}
> +static inline u32 host1x_sync_cfpeek_ptrs_cf_rd_ptr_s(void)
> +{
> +	return 9;
> +}
> +static inline u32 host1x_sync_cfpeek_ptrs_cf_rd_ptr_f(u32 v)
> +{
> +	return (v & 0x1ff) << 0;
> +}
> +static inline u32 host1x_sync_cfpeek_ptrs_cf_rd_ptr_m(void)
> +{
> +	return 0x1ff << 0;
> +}
> +static inline u32 host1x_sync_cfpeek_ptrs_cf_rd_ptr_v(u32 r)
> +{
> +	return (r >> 0) & 0x1ff;
> +}
> +static inline u32 host1x_sync_cfpeek_ptrs_cf_wr_ptr_s(void)
> +{
> +	return 9;
> +}
> +static inline u32 host1x_sync_cfpeek_ptrs_cf_wr_ptr_f(u32 v)
> +{
> +	return (v & 0x1ff) << 16;
> +}
> +static inline u32 host1x_sync_cfpeek_ptrs_cf_wr_ptr_m(void)
> +{
> +	return 0x1ff << 16;
> +}
> +static inline u32 host1x_sync_cfpeek_ptrs_cf_wr_ptr_v(u32 r)
> +{
> +	return (r >> 16) & 0x1ff;
> +}
> +static inline u32 host1x_sync_cbstat_0_r(void)
> +{
> +	return 0x758;
> +}
> +static inline u32 host1x_sync_cbstat_0_cboffset0_s(void)
> +{
> +	return 16;
> +}
> +static inline u32 host1x_sync_cbstat_0_cboffset0_f(u32 v)
> +{
> +	return (v & 0xffff) << 0;
> +}
> +static inline u32 host1x_sync_cbstat_0_cboffset0_m(void)
> +{
> +	return 0xffff << 0;
> +}
> +static inline u32 host1x_sync_cbstat_0_cboffset0_v(u32 r)
> +{
> +	return (r >> 0) & 0xffff;
> +}
> +static inline u32 host1x_sync_cbstat_0_cbclass0_s(void)
> +{
> +	return 10;
> +}
> +static inline u32 host1x_sync_cbstat_0_cbclass0_f(u32 v)
> +{
> +	return (v & 0x3ff) << 16;
> +}
> +static inline u32 host1x_sync_cbstat_0_cbclass0_m(void)
> +{
> +	return 0x3ff << 16;
> +}
> +static inline u32 host1x_sync_cbstat_0_cbclass0_v(u32 r)
> +{
> +	return (r >> 16) & 0x3ff;
> +}
> +
> +#endif /* __hw_host1x_sync_host1x_h__ */
> diff --git a/drivers/video/tegra/host/host1x/hw_host1x01_uclass.h b/drivers/video/tegra/host/host1x/hw_host1x01_uclass.h
> new file mode 100644
> index 0000000..ed6e4b7
> --- /dev/null
> +++ b/drivers/video/tegra/host/host1x/hw_host1x01_uclass.h
> @@ -0,0 +1,474 @@
> +/*
> + * drivers/video/tegra/host/host1x/hw_host1x_uclass_host1x.h
> + *
> + * Copyright (c) 2012, NVIDIA Corporation.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
> + *
> + */
> +
> + /*
> +  * Function naming determines intended use:
> +  *
> +  *     <x>_r(void) : Returns the offset for register <x>.
> +  *
> +  *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
> +  *
> +  *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
> +  *
> +  *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
> +  *         and masked to place it at field <y> of register <x>.  This value
> +  *         can be |'d with others to produce a full register value for
> +  *         register <x>.
> +  *
> +  *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
> +  *         value can be ~'d and then &'d to clear the value of field <y> for
> +  *         register <x>.
> +  *
> +  *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
> +  *         to place it at field <y> of register <x>.  This value can be |'d
> +  *         with others to produce a full register value for <x>.
> +  *
> +  *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
> +  *         <x> value 'r' after being shifted to place its LSB at bit 0.
> +  *         This value is suitable for direct comparison with other unshifted
> +  *         values appropriate for use in field <y> of register <x>.
> +  *
> +  *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
> +  *         field <y> of register <x>.  This value is suitable for direct
> +  *         comparison with unshifted values appropriate for use in field <y>
> +  *         of register <x>.
> +  */
> +
> +#ifndef __hw_host1x_uclass_host1x_h__
> +#define __hw_host1x_uclass_host1x_h__
> +/*This file is autogenerated.  Do not edit. */
> +
> +static inline u32 host1x_uclass_incr_syncpt_r(void)
> +{
> +	return 0x0;
> +}
> +static inline u32 host1x_uclass_incr_syncpt_cond_s(void)
> +{
> +	return 8;
> +}
> +static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v)
> +{
> +	return (v & 0xff) << 8;
> +}
> +static inline u32 host1x_uclass_incr_syncpt_cond_m(void)
> +{
> +	return 0xff << 8;
> +}
> +static inline u32 host1x_uclass_incr_syncpt_cond_v(u32 r)
> +{
> +	return (r >> 8) & 0xff;
> +}
> +static inline u32 host1x_uclass_incr_syncpt_cond_immediate_v(void)
> +{
> +	return 0;
> +}
> +static inline u32 host1x_uclass_incr_syncpt_cond_op_done_v(void)
> +{
> +	return 1;
> +}
> +static inline u32 host1x_uclass_incr_syncpt_cond_rd_done_v(void)
> +{
> +	return 2;
> +}
> +static inline u32 host1x_uclass_incr_syncpt_cond_reg_wr_safe_v(void)
> +{
> +	return 3;
> +}
> +static inline u32 host1x_uclass_incr_syncpt_indx_s(void)
> +{
> +	return 8;
> +}
> +static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v)
> +{
> +	return (v & 0xff) << 0;
> +}
> +static inline u32 host1x_uclass_incr_syncpt_indx_m(void)
> +{
> +	return 0xff << 0;
> +}
> +static inline u32 host1x_uclass_incr_syncpt_indx_v(u32 r)
> +{
> +	return (r >> 0) & 0xff;
> +}
> +static inline u32 host1x_uclass_wait_syncpt_r(void)
> +{
> +	return 0x8;
> +}
> +static inline u32 host1x_uclass_wait_syncpt_indx_s(void)
> +{
> +	return 8;
> +}
> +static inline u32 host1x_uclass_wait_syncpt_indx_f(u32 v)
> +{
> +	return (v & 0xff) << 24;
> +}
> +static inline u32 host1x_uclass_wait_syncpt_indx_m(void)
> +{
> +	return 0xff << 24;
> +}
> +static inline u32 host1x_uclass_wait_syncpt_indx_v(u32 r)
> +{
> +	return (r >> 24) & 0xff;
> +}
> +static inline u32 host1x_uclass_wait_syncpt_thresh_s(void)
> +{
> +	return 24;
> +}
> +static inline u32 host1x_uclass_wait_syncpt_thresh_f(u32 v)
> +{
> +	return (v & 0xffffff) << 0;
> +}
> +static inline u32 host1x_uclass_wait_syncpt_thresh_m(void)
> +{
> +	return 0xffffff << 0;
> +}
> +static inline u32 host1x_uclass_wait_syncpt_thresh_v(u32 r)
> +{
> +	return (r >> 0) & 0xffffff;
> +}
> +static inline u32 host1x_uclass_wait_syncpt_base_r(void)
> +{
> +	return 0x9;
> +}
> +static inline u32 host1x_uclass_wait_syncpt_base_indx_s(void)
> +{
> +	return 8;
> +}
> +static inline u32 host1x_uclass_wait_syncpt_base_indx_f(u32 v)
> +{
> +	return (v & 0xff) << 24;
> +}
> +static inline u32 host1x_uclass_wait_syncpt_base_indx_m(void)
> +{
> +	return 0xff << 24;
> +}
> +static inline u32 host1x_uclass_wait_syncpt_base_indx_v(u32 r)
> +{
> +	return (r >> 24) & 0xff;
> +}
> +static inline u32 host1x_uclass_wait_syncpt_base_base_indx_s(void)
> +{
> +	return 8;
> +}
> +static inline u32 host1x_uclass_wait_syncpt_base_base_indx_f(u32 v)
> +{
> +	return (v & 0xff) << 16;
> +}
> +static inline u32 host1x_uclass_wait_syncpt_base_base_indx_m(void)
> +{
> +	return 0xff << 16;
> +}
> +static inline u32 host1x_uclass_wait_syncpt_base_base_indx_v(u32 r)
> +{
> +	return (r >> 16) & 0xff;
> +}
> +static inline u32 host1x_uclass_wait_syncpt_base_offset_s(void)
> +{
> +	return 16;
> +}
> +static inline u32 host1x_uclass_wait_syncpt_base_offset_f(u32 v)
> +{
> +	return (v & 0xffff) << 0;
> +}
> +static inline u32 host1x_uclass_wait_syncpt_base_offset_m(void)
> +{
> +	return 0xffff << 0;
> +}
> +static inline u32 host1x_uclass_wait_syncpt_base_offset_v(u32 r)
> +{
> +	return (r >> 0) & 0xffff;
> +}
> +static inline u32 host1x_uclass_load_syncpt_base_r(void)
> +{
> +	return 0xb;
> +}
> +static inline u32 host1x_uclass_load_syncpt_base_base_indx_s(void)
> +{
> +	return 8;
> +}
> +static inline u32 host1x_uclass_load_syncpt_base_base_indx_f(u32 v)
> +{
> +	return (v & 0xff) << 24;
> +}
> +static inline u32 host1x_uclass_load_syncpt_base_base_indx_m(void)
> +{
> +	return 0xff << 24;
> +}
> +static inline u32 host1x_uclass_load_syncpt_base_base_indx_v(u32 r)
> +{
> +	return (r >> 24) & 0xff;
> +}
> +static inline u32 host1x_uclass_load_syncpt_base_value_s(void)
> +{
> +	return 24;
> +}
> +static inline u32 host1x_uclass_load_syncpt_base_value_f(u32 v)
> +{
> +	return (v & 0xffffff) << 0;
> +}
> +static inline u32 host1x_uclass_load_syncpt_base_value_m(void)
> +{
> +	return 0xffffff << 0;
> +}
> +static inline u32 host1x_uclass_load_syncpt_base_value_v(u32 r)
> +{
> +	return (r >> 0) & 0xffffff;
> +}
> +static inline u32 host1x_uclass_incr_syncpt_base_r(void)
> +{
> +	return 0xc;
> +}
> +static inline u32 host1x_uclass_incr_syncpt_base_base_indx_s(void)
> +{
> +	return 8;
> +}
> +static inline u32 host1x_uclass_incr_syncpt_base_base_indx_f(u32 v)
> +{
> +	return (v & 0xff) << 24;
> +}
> +static inline u32 host1x_uclass_incr_syncpt_base_base_indx_m(void)
> +{
> +	return 0xff << 24;
> +}
> +static inline u32 host1x_uclass_incr_syncpt_base_base_indx_v(u32 r)
> +{
> +	return (r >> 24) & 0xff;
> +}
> +static inline u32 host1x_uclass_incr_syncpt_base_offset_s(void)
> +{
> +	return 24;
> +}
> +static inline u32 host1x_uclass_incr_syncpt_base_offset_f(u32 v)
> +{
> +	return (v & 0xffffff) << 0;
> +}
> +static inline u32 host1x_uclass_incr_syncpt_base_offset_m(void)
> +{
> +	return 0xffffff << 0;
> +}
> +static inline u32 host1x_uclass_incr_syncpt_base_offset_v(u32 r)
> +{
> +	return (r >> 0) & 0xffffff;
> +}
> +static inline u32 host1x_uclass_indoff_r(void)
> +{
> +	return 0x2d;
> +}
> +static inline u32 host1x_uclass_indoff_indbe_s(void)
> +{
> +	return 4;
> +}
> +static inline u32 host1x_uclass_indoff_indbe_f(u32 v)
> +{
> +	return (v & 0xf) << 28;
> +}
> +static inline u32 host1x_uclass_indoff_indbe_m(void)
> +{
> +	return 0xf << 28;
> +}
> +static inline u32 host1x_uclass_indoff_indbe_v(u32 r)
> +{
> +	return (r >> 28) & 0xf;
> +}
> +static inline u32 host1x_uclass_indoff_autoinc_s(void)
> +{
> +	return 1;
> +}
> +static inline u32 host1x_uclass_indoff_autoinc_f(u32 v)
> +{
> +	return (v & 0x1) << 27;
> +}
> +static inline u32 host1x_uclass_indoff_autoinc_m(void)
> +{
> +	return 0x1 << 27;
> +}
> +static inline u32 host1x_uclass_indoff_autoinc_v(u32 r)
> +{
> +	return (r >> 27) & 0x1;
> +}
> +static inline u32 host1x_uclass_indoff_spool_s(void)
> +{
> +	return 1;
> +}
> +static inline u32 host1x_uclass_indoff_spool_f(u32 v)
> +{
> +	return (v & 0x1) << 26;
> +}
> +static inline u32 host1x_uclass_indoff_spool_m(void)
> +{
> +	return 0x1 << 26;
> +}
> +static inline u32 host1x_uclass_indoff_spool_v(u32 r)
> +{
> +	return (r >> 26) & 0x1;
> +}
> +static inline u32 host1x_uclass_indoff_indoffset_s(void)
> +{
> +	return 24;
> +}
> +static inline u32 host1x_uclass_indoff_indoffset_f(u32 v)
> +{
> +	return (v & 0xffffff) << 2;
> +}
> +static inline u32 host1x_uclass_indoff_indoffset_m(void)
> +{
> +	return 0xffffff << 2;
> +}
> +static inline u32 host1x_uclass_indoff_indoffset_v(u32 r)
> +{
> +	return (r >> 2) & 0xffffff;
> +}
> +static inline u32 host1x_uclass_indoff_indmodid_s(void)
> +{
> +	return 8;
> +}
> +static inline u32 host1x_uclass_indoff_indmodid_f(u32 v)
> +{
> +	return (v & 0xff) << 18;
> +}
> +static inline u32 host1x_uclass_indoff_indmodid_m(void)
> +{
> +	return 0xff << 18;
> +}
> +static inline u32 host1x_uclass_indoff_indmodid_v(u32 r)
> +{
> +	return (r >> 18) & 0xff;
> +}
> +static inline u32 host1x_uclass_indoff_indmodid_host1x_v(void)
> +{
> +	return 0;
> +}
> +static inline u32 host1x_uclass_indoff_indmodid_mpe_v(void)
> +{
> +	return 1;
> +}
> +static inline u32 host1x_uclass_indoff_indmodid_vi_v(void)
> +{
> +	return 2;
> +}
> +static inline u32 host1x_uclass_indoff_indmodid_epp_v(void)
> +{
> +	return 3;
> +}
> +static inline u32 host1x_uclass_indoff_indmodid_isp_v(void)
> +{
> +	return 4;
> +}
> +static inline u32 host1x_uclass_indoff_indmodid_gr2d_v(void)
> +{
> +	return 5;
> +}
> +static inline u32 host1x_uclass_indoff_indmodid_gr3d_v(void)
> +{
> +	return 6;
> +}
> +static inline u32 host1x_uclass_indoff_indmodid_display_v(void)
> +{
> +	return 8;
> +}
> +static inline u32 host1x_uclass_indoff_indmodid_tvo_v(void)
> +{
> +	return 11;
> +}
> +static inline u32 host1x_uclass_indoff_indmodid_displayb_v(void)
> +{
> +	return 9;
> +}
> +static inline u32 host1x_uclass_indoff_indmodid_dsi_v(void)
> +{
> +	return 12;
> +}
> +static inline u32 host1x_uclass_indoff_indmodid_hdmi_v(void)
> +{
> +	return 10;
> +}
> +static inline u32 host1x_uclass_indoff_indmodid_dsib_v(void)
> +{
> +	return 16;
> +}
> +static inline u32 host1x_uclass_indoff_indroffset_s(void)
> +{
> +	return 16;
> +}
> +static inline u32 host1x_uclass_indoff_indroffset_f(u32 v)
> +{
> +	return (v & 0xffff) << 2;
> +}
> +static inline u32 host1x_uclass_indoff_indroffset_m(void)
> +{
> +	return 0xffff << 2;
> +}
> +static inline u32 host1x_uclass_indoff_indroffset_v(u32 r)
> +{
> +	return (r >> 2) & 0xffff;
> +}
> +static inline u32 host1x_uclass_indoff_acctype_s(void)
> +{
> +	return 1;
> +}
> +static inline u32 host1x_uclass_indoff_acctype_f(u32 v)
> +{
> +	return (v & 0x1) << 1;
> +}
> +static inline u32 host1x_uclass_indoff_acctype_m(void)
> +{
> +	return 0x1 << 1;
> +}
> +static inline u32 host1x_uclass_indoff_acctype_v(u32 r)
> +{
> +	return (r >> 1) & 0x1;
> +}
> +static inline u32 host1x_uclass_indoff_acctype_reg_v(void)
> +{
> +	return 0;
> +}
> +static inline u32 host1x_uclass_indoff_acctype_fb_v(void)
> +{
> +	return 1;
> +}
> +static inline u32 host1x_uclass_indoff_rwn_s(void)
> +{
> +	return 1;
> +}
> +static inline u32 host1x_uclass_indoff_rwn_f(u32 v)
> +{
> +	return (v & 0x1) << 0;
> +}
> +static inline u32 host1x_uclass_indoff_rwn_m(void)
> +{
> +	return 0x1 << 0;
> +}
> +static inline u32 host1x_uclass_indoff_rwn_v(u32 r)
> +{
> +	return (r >> 0) & 0x1;
> +}
> +static inline u32 host1x_uclass_indoff_rwn_write_v(void)
> +{
> +	return 0;
> +}
> +static inline u32 host1x_uclass_indoff_rwn_read_v(void)
> +{
> +	return 1;
> +}
> +static inline u32 host1x_uclass_inddata_r(void)
> +{
> +	return 0x2e;
> +}
> +
> +#endif /* __hw_host1x_uclass_host1x_h__ */
[...]

This is a joke, right?

Thierry

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