From mboxrd@z Thu Jan 1 00:00:00 1970 From: andrew@lunn.ch (Andrew Lunn) Date: Fri, 28 Dec 2012 18:56:18 +0100 Subject: [PATCH] cpuidle: kirkwood: Move out of mach directory, add DT. In-Reply-To: <50DDDBEB.3000002@ti.com> References: <1356698844-4220-1-git-send-email-andrew@lunn.ch> <50DDAA42.2020101@gmail.com> <20121228143517.GA5172@lunn.ch> <50DDB2E3.103@gmail.com> <20121228154927.GC5172@lunn.ch> <50DDC54A.3020509@gmail.com> <50DDCF47.1030305@ti.com> <20121228172807.GA7578@lunn.ch> <50DDDBEB.3000002@ti.com> Message-ID: <20121228175618.GC7578@lunn.ch> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org > Is this single CPU or multi-cpu machine ? Its a uniprocessor. > Even though the cpu_do_idle() > has just couple of instructions, there can be lot more happening in > background especially with multi masters system. It might be safe if the > single CPU is the only master accessing DDR. In multi-master, multi-CPU > scenario though it can't work reliably. There are DMA engines which could be active, moving stuff into/out of memory. Having said that, this code is not new, it is just getting a new home. There has not been problems before. Having this 256 cycle delay etc, suggests the hardware design is robust. Andrew From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andrew Lunn Subject: Re: [PATCH] cpuidle: kirkwood: Move out of mach directory, add DT. Date: Fri, 28 Dec 2012 18:56:18 +0100 Message-ID: <20121228175618.GC7578@lunn.ch> References: <1356698844-4220-1-git-send-email-andrew@lunn.ch> <50DDAA42.2020101@gmail.com> <20121228143517.GA5172@lunn.ch> <50DDB2E3.103@gmail.com> <20121228154927.GC5172@lunn.ch> <50DDC54A.3020509@gmail.com> <50DDCF47.1030305@ti.com> <20121228172807.GA7578@lunn.ch> <50DDDBEB.3000002@ti.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Content-Disposition: inline In-Reply-To: <50DDDBEB.3000002-l0cyMroinI0@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: devicetree-discuss-bounces+gldd-devicetree-discuss=m.gmane.org-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org Sender: "devicetree-discuss" To: Santosh Shilimkar Cc: Andrew Lunn , Jason Cooper , len.brown-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org, devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org, rafael.j.wysocki-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org, linux ARM List-Id: devicetree@vger.kernel.org > Is this single CPU or multi-cpu machine ? Its a uniprocessor. > Even though the cpu_do_idle() > has just couple of instructions, there can be lot more happening in > background especially with multi masters system. It might be safe if the > single CPU is the only master accessing DDR. In multi-master, multi-CPU > scenario though it can't work reliably. There are DMA engines which could be active, moving stuff into/out of memory. Having said that, this code is not new, it is just getting a new home. There has not been problems before. Having this 256 cycle delay etc, suggests the hardware design is robust. Andrew