From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH v2] drm/i915: HDMI/DP - ELD info refresh support for Haswell Date: Fri, 18 Jan 2013 15:13:59 +0200 Message-ID: <20130118131359.GY3503@intel.com> References: <1358477515-7323-1-git-send-email-xingchao.wang@intel.com> <20130118104535.GV3503@intel.com> <46B810F6945F7C4788E11DCE57EC48900FFC9627@SHSMSX102.ccr.corp.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga14.intel.com (mga14.intel.com [143.182.124.37]) by gabe.freedesktop.org (Postfix) with ESMTP id E939EE5C53 for ; Fri, 18 Jan 2013 05:14:03 -0800 (PST) Content-Disposition: inline In-Reply-To: <46B810F6945F7C4788E11DCE57EC48900FFC9627@SHSMSX102.ccr.corp.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: "Wang, Xingchao" Cc: "daniel.vetter@ffwll.ch" , "intel-gfx@lists.freedesktop.org" , "Zanoni, Paulo R" List-Id: intel-gfx@lists.freedesktop.org On Fri, Jan 18, 2013 at 12:00:10PM +0000, Wang, Xingchao wrote: > = > > -----Original Message----- > > From: Ville Syrj=E4l=E4 [mailto:ville.syrjala@linux.intel.com] > > Sent: Friday, January 18, 2013 6:46 PM > > To: Wang, Xingchao > > Cc: intel-gfx@lists.freedesktop.org; daniel.vetter@ffwll.ch; Zanoni, Pa= ulo R > > Subject: Re: [Intel-gfx] [PATCH v2] drm/i915: HDMI/DP - ELD info refresh > > support for Haswell > > = > > On Fri, Jan 18, 2013 at 10:51:55AM +0800, Wang Xingchao wrote: > > > ELD info should be updated dynamically according to hot plug event. > > > For haswell chip, clear/set the eld valid bit and output enable bit > > > from callback intel_disable/eanble_ddi(). > > = > > Hmm. Is it OK to set the ELD valid bit if the ELD hasn't actually been = written? > = > This triggers an unsolicited event to ALSA driver which continue to read = ELD info. I take it we don't want that to happen? > > And besides these bits are already set by haswell_write_eld(). > = > Intel_disable/enable_ddi() was called even after haswell_write_eld(), so = we need set the bits again. For the mode set sequence only intel_enable_ddi() is called after haswell_write_eld(). This is how the sequence should end up looking with the current code: intel_set_mode() -> haswell_crtc_disable() -> intel_disable_ddi() -> intel_crtc_mode_set() -> haswell_crtc_mode_set() -> intel_ddi_mode_set() -> intel_write_eld() -> haswell_write_eld() -> haswell_crtc_enable() -> intel_enable_ddi() But for DPMS on->off->on there would be calls to haswell_crtc_disable() and haswell_crtc_enable() w/o calls to haswell_write_eld(). I suppose this is the problem you want to fix? So, perhaps there should be a flag somewhere that would be cleared at the beginning of the mode_set operation, and then intel_write_eld() should set the flag when the ELD was written succesfully. intel_enable_ddi() could check the flag and only set the ELD valid bit when the flag is set. Should non-ddi platforms do something similar as well? > Thanks > --xingchao > > = > > > > > > Signed-off-by: Wang Xingchao > > > --- > > > drivers/gpu/drm/i915/intel_ddi.c | 18 ++++++++++++++++++ > > > 1 file changed, 18 insertions(+) > > > > > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c > > > b/drivers/gpu/drm/i915/intel_ddi.c > > > index f02b3fe..7ce4728 100644 > > > --- a/drivers/gpu/drm/i915/intel_ddi.c > > > +++ b/drivers/gpu/drm/i915/intel_ddi.c > > > @@ -1274,10 +1274,14 @@ static void intel_ddi_post_disable(struct > > > intel_encoder *intel_encoder) static void intel_enable_ddi(struct > > > intel_encoder *intel_encoder) { > > > struct drm_encoder *encoder =3D &intel_encoder->base; > > > + struct drm_crtc *crtc =3D encoder->crtc; > > > + struct intel_crtc *intel_crtc =3D to_intel_crtc(crtc); > > > + int pipe =3D intel_crtc->pipe; > > > struct drm_device *dev =3D encoder->dev; > > > struct drm_i915_private *dev_priv =3D dev->dev_private; > > > enum port port =3D intel_ddi_get_encoder_port(intel_encoder); > > > int type =3D intel_encoder->type; > > > + int tmp; > > > > > > if (type =3D=3D INTEL_OUTPUT_HDMI) { > > > /* In HDMI/DVI mode, the port width, and swing/emphasis values > > @@ > > > -1290,18 +1294,32 @@ static void intel_enable_ddi(struct intel_encoder > > > *intel_encoder) > > > > > > ironlake_edp_backlight_on(intel_dp); > > > } > > > + > > > + tmp =3D I915_READ(HSW_AUD_PIN_ELD_CP_VLD); > > > + tmp |=3D ((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * > > 4)); > > > + I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); > > > } > > > > > > static void intel_disable_ddi(struct intel_encoder *intel_encoder) { > > > struct drm_encoder *encoder =3D &intel_encoder->base; > > > + struct drm_crtc *crtc =3D encoder->crtc; > > > + struct intel_crtc *intel_crtc =3D to_intel_crtc(crtc); > > > + int pipe =3D intel_crtc->pipe; > > > int type =3D intel_encoder->type; > > > + struct drm_device *dev =3D encoder->dev; > > > + struct drm_i915_private *dev_priv =3D dev->dev_private; > > > + int tmp; > > > > > > if (type =3D=3D INTEL_OUTPUT_EDP) { > > > struct intel_dp *intel_dp =3D enc_to_intel_dp(encoder); > > > > > > ironlake_edp_backlight_off(intel_dp); > > > } > > > + > > > + tmp =3D I915_READ(HSW_AUD_PIN_ELD_CP_VLD); > > > + tmp &=3D ~((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * > > 4)); > > > + I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); > > > } > > > > > > int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv) > > > -- > > > 1.7.9.5 > > > > > > _______________________________________________ > > > Intel-gfx mailing list > > > Intel-gfx@lists.freedesktop.org > > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > = > > -- > > Ville Syrj=E4l=E4 > > Intel OTC -- = Ville Syrj=E4l=E4 Intel OTC