From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 08/33] drm/i915: SWF screatch registers need an offset on VLV Date: Thu, 24 Jan 2013 22:37:28 +0100 Message-ID: <20130124213728.GG31306@phenom.ffwll.local> References: <1359034198-19678-1-git-send-email-ville.syrjala@linux.intel.com> <1359034198-19678-9-git-send-email-ville.syrjala@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-ee0-f41.google.com (mail-ee0-f41.google.com [74.125.83.41]) by gabe.freedesktop.org (Postfix) with ESMTP id E37BAE5DBD for ; Thu, 24 Jan 2013 13:35:23 -0800 (PST) Received: by mail-ee0-f41.google.com with SMTP id c13so5008201eek.28 for ; Thu, 24 Jan 2013 13:35:23 -0800 (PST) Content-Disposition: inline In-Reply-To: <1359034198-19678-9-git-send-email-ville.syrjala@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: ville.syrjala@linux.intel.com Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Thu, Jan 24, 2013 at 03:29:33PM +0200, ville.syrjala@linux.intel.com wro= te: > From: Ville Syrj=E4l=E4 > = > Signed-off-by: Ville Syrj=E4l=E4 It's true that we safe/restore these suckers across suspend/resume, but I have no idea why or whether we need to. Since there's no way we'll ever support ums on vlv I think we should just try to guard the safe/resume code with DRIVER_MODESET checks and drop this chunk here. Or too risky? -Daniel > --- > drivers/gpu/drm/i915/i915_reg.h | 26 +++++++++++++------------- > 1 file changed, 13 insertions(+), 13 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_= reg.h > index 80f9b6a..87eed0c 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -3046,19 +3046,19 @@ > (I915_WRITE((reg), (gfx_addr) | I915_LO_DISPBASE(I915_READ(reg)))) > = > /* VBIOS flags */ > -#define SWF00 0x71410 > -#define SWF01 0x71414 > -#define SWF02 0x71418 > -#define SWF03 0x7141c > -#define SWF04 0x71420 > -#define SWF05 0x71424 > -#define SWF06 0x71428 > -#define SWF10 0x70410 > -#define SWF11 0x70414 > -#define SWF14 0x71420 > -#define SWF30 0x72414 > -#define SWF31 0x72418 > -#define SWF32 0x7241c > +#define SWF00 (dev_priv->info->display_mmio_offset + 0x71410) > +#define SWF01 (dev_priv->info->display_mmio_offset + 0x71414) > +#define SWF02 (dev_priv->info->display_mmio_offset + 0x71418) > +#define SWF03 (dev_priv->info->display_mmio_offset + 0x7141c) > +#define SWF04 (dev_priv->info->display_mmio_offset + 0x71420) > +#define SWF05 (dev_priv->info->display_mmio_offset + 0x71424) > +#define SWF06 (dev_priv->info->display_mmio_offset + 0x71428) > +#define SWF10 (dev_priv->info->display_mmio_offset + 0x70410) > +#define SWF11 (dev_priv->info->display_mmio_offset + 0x70414) > +#define SWF14 (dev_priv->info->display_mmio_offset + 0x71420) > +#define SWF30 (dev_priv->info->display_mmio_offset + 0x72414) > +#define SWF31 (dev_priv->info->display_mmio_offset + 0x72418) > +#define SWF32 (dev_priv->info->display_mmio_offset + 0x7241c) > = > /* Pipe B */ > #define _PIPEBDSL 0x71000 > -- = > 1.7.12.4 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch