From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 22/33] drm/i915: Pipe palette registers need an offset on VLV Date: Thu, 24 Jan 2013 23:22:15 +0100 Message-ID: <20130124222215.GD23080@phenom.ffwll.local> References: <1359034198-19678-1-git-send-email-ville.syrjala@linux.intel.com> <1359034198-19678-23-git-send-email-ville.syrjala@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-ea0-f182.google.com (mail-ea0-f182.google.com [209.85.215.182]) by gabe.freedesktop.org (Postfix) with ESMTP id C4AB1E5BF4 for ; Thu, 24 Jan 2013 14:20:12 -0800 (PST) Received: by mail-ea0-f182.google.com with SMTP id a12so4232890eaa.41 for ; Thu, 24 Jan 2013 14:20:12 -0800 (PST) Content-Disposition: inline In-Reply-To: <1359034198-19678-23-git-send-email-ville.syrjala@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: ville.syrjala@linux.intel.com Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Thu, Jan 24, 2013 at 03:29:47PM +0200, ville.syrjala@linux.intel.com wro= te: > From: Ville Syrj=E4l=E4 > = > Signed-off-by: Ville Syrj=E4l=E4 I've noticed that the PALETTE moved around a bit for pch-split platforms already, but otoh the palette support is quite enhanced there already, and we don't bother with it. Which renders 10bpc a bit pointless. So I'll gulp this one here. -Daniel > --- > drivers/gpu/drm/i915/i915_reg.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_= reg.h > index 15ecded..7c71622 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1169,8 +1169,8 @@ > * Palette regs > */ > = > -#define _PALETTE_A 0x0a000 > -#define _PALETTE_B 0x0a800 > +#define _PALETTE_A (dev_priv->info->display_mmio_offset + 0xa000) > +#define _PALETTE_B (dev_priv->info->display_mmio_offset + 0xa800) > #define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B) > = > /* MCH MMIO space */ > -- = > 1.7.12.4 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch