From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 04/22] drm/i915: implement WaGTEnableMiFlush on VLV Date: Tue, 5 Feb 2013 17:31:02 +0200 Message-ID: <20130205153102.GX9135@intel.com> References: <1359809786-26434-1-git-send-email-jbarnes@virtuousgeek.org> <1359809786-26434-5-git-send-email-jbarnes@virtuousgeek.org> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga14.intel.com (mga14.intel.com [143.182.124.37]) by gabe.freedesktop.org (Postfix) with ESMTP id B1EC9E5ED4 for ; Tue, 5 Feb 2013 07:31:06 -0800 (PST) Content-Disposition: inline In-Reply-To: <1359809786-26434-5-git-send-email-jbarnes@virtuousgeek.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Jesse Barnes Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Sat, Feb 02, 2013 at 01:56:08PM +0100, Jesse Barnes wrote: > We don't generally use MI_FLUSH these days, but this bit may affect > other flushing logic, so set it to be safe. > = > Signed-off-by: Jesse Barnes > --- > drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++ > 1 file changed, 3 insertions(+) > = > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i9= 15/intel_ringbuffer.c > index 2bd074a..5a9e26a 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -511,6 +511,9 @@ static int init_render_ring(struct intel_ring_buffer = *ring) > I915_WRITE(GFX_MODE_GEN7, > _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) | > _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); > + if (IS_VALLEYVIEW(dev)) > + I915_WRITE(MI_MODE, I915_READ(MI_MODE) | > + _MASKED_BIT_ENABLE(MI_FLUSH_ENABLE)); Include a comment with the WA name? Also this WA seems to be present since SNB. So should the check be for 'gen>=3D6' instead of VLV? Hmm. It seems that used to be the case actually and then the WA was removed in commit: commit 8d79c3490aecfe6e51f0ba6f9780746fb1434954 Author: Eric Anholt Date: Thu Jan 19 10:50:05 2012 -0800 drm/i915: Remove the MI_FLUSH_ENABLE setting. = We have always been using the wrong bit -- it's bit 12. However, the bit also doesn't do anything -- hardware has always accepted the MI_FLUSH command even when it was specced not to. = Given that there is only one MI_FLUSH emitted in all of the driver stack on gen6+ (in i965_video.c of the 2d driver, and it should be using other code to do its flush instead), just remove the MI_FLUSH enable instead of trying to fix it. = Signed-off-by: Eric Anholt Reviewed-by: Kenneth Graunke Reviewed-by: Ben Widawsky Signed-off-by: Daniel Vetter Looks like the wrong bit part was fixed at some point. This patch needs to be refreshed anyway since the code was shuffled around a bit. > } > = > if (INTEL_INFO(dev)->gen >=3D 5) { > -- = > 1.7.9.5 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC