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Date: Tue, 5 Feb 2013 20:09:02 +0100
From: Andi Kleen <andi@firstfloor.org>
To: Stephane Eranian <eranian@google.com>
Cc: Andi Kleen <andi@firstfloor.org>, Ingo Molnar <mingo@kernel.org>,
        LKML <linux-kernel@vger.kernel.org>,
        Peter Zijlstra <a.p.zijlstra@chello.nl>,
        Andrew Morton <akpm@linux-foundation.org>,
        Arnaldo Carvalho de Melo <acme@redhat.com>,
        Jiri Olsa <jolsa@redhat.com>, Namhyung Kim <namhyung@kernel.org>,
        Andi Kleen <ak@linux.intel.com>
Subject: Re: [PATCH 4/5] perf, x86: Support full width counting
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On Tue, Feb 05, 2013 at 04:15:26PM +0100, Stephane Eranian wrote:
> > --- a/arch/x86/kernel/cpu/perf_event_intel.c
> > +++ b/arch/x86/kernel/cpu/perf_event_intel.c
> > @@ -2228,5 +2228,11 @@ __init int intel_pmu_init(void)
> >                 }
> >         }
> >
> > +       /* Support full width counters using alternative MSR range */
> > +       if (x86_pmu.intel_cap.fw_write) {
> > +               x86_pmu.max_period = x86_pmu.cntval_mask;
> 
> Something is not clear to me: What happens to the fixed counters with
> full writes? Were they already full-width? The SDM does not explain what
> happens to them with this extension. Could you clarify?

I tested and they always support the full reported width.

-Andi

-- 
ak@linux.intel.com -- Speaking for myself only.