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From: Ingo Molnar <mingo@kernel.org>
To: Jacob Shin <jacob.shin@amd.com>
Cc: Thomas Gleixner <tglx@linutronix.de>,
	Ingo Molnar <mingo@redhat.com>, "H. Peter Anvin" <hpa@zytor.com>,
	x86@kernel.org, Peter Zijlstra <a.p.zijlstra@chello.nl>,
	Paul Mackerras <paulus@samba.org>,
	Arnaldo Carvalho de Melo <acme@ghostprotocols.net>,
	Stephane Eranian <eranian@google.com>,
	Jiri Olsa <jolsa@redhat.com>,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH 6/6] perf, amd: Enable northbridge performance counters on AMD family 15h
Date: Thu, 7 Feb 2013 20:09:21 +0100	[thread overview]
Message-ID: <20130207190921.GC25223@gmail.com> (raw)
In-Reply-To: <20130207175703.GA3398@jshin-Toonie>


* Jacob Shin <jacob.shin@amd.com> wrote:

> On Wed, Feb 06, 2013 at 11:26:29AM -0600, Jacob Shin wrote:
> > On AMD family 15h processors, there are 4 new performance counters
> > (in addition to 6 core performance counters) that can be used for
> > counting northbridge events (i.e. DRAM accesses). Their bit fields are
> > almost identical to the core performance counters. However, unlike the
> > core performance counters, these MSRs are shared between multiple
> > cores (that share the same northbridge). We will reuse the same code
> > path as existing family 10h northbridge event constraints handler
> > logic to enforce this sharing.
> > 
> > Signed-off-by: Jacob Shin <jacob.shin@amd.com>
> 
> Hi Ingo, could you please apply this one to tip as well? I 
> recieved tip-bot emails for all other patches in this series 
> except for this last one 6/6.
> 
> Or was that intentional? If so, what other changes are 
> required/ recommended?

Was waiting for Stephane's ack.

Thanks,

	Ingo

  parent reply	other threads:[~2013-02-07 19:09 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-02-06 17:26 [PATCH V6 0/6] perf, amd: Enable AMD family 15h northbridge counters Jacob Shin
2013-02-06 17:26 ` [PATCH 1/6] perf, amd: Rework northbridge event constraints handler Jacob Shin
2013-02-06 20:28   ` [tip:perf/core] perf/x86/amd: " tip-bot for Robert Richter
2013-02-06 17:26 ` [PATCH 2/6] perf, amd: Generalize northbridge constraints code for family 15h Jacob Shin
2013-02-06 20:29   ` [tip:perf/core] perf/x86/amd: " tip-bot for Robert Richter
2013-02-06 17:26 ` [PATCH 3/6] perf, amd: Use proper naming scheme for AMD bit field definitions Jacob Shin
2013-02-06 20:30   ` [tip:perf/core] perf/x86/amd: " tip-bot for Jacob Shin
2013-02-06 17:26 ` [PATCH 4/6] perf, x86: Move MSR address offset calculation to architecture specific files Jacob Shin
2013-02-06 20:31   ` [tip:perf/core] perf/x86: " tip-bot for Jacob Shin
2013-02-06 17:26 ` [PATCH 5/6] perf, x86: Allow for architecture specific RDPMC indexes Jacob Shin
2013-02-06 20:32   ` [tip:perf/core] perf/x86: " tip-bot for Jacob Shin
2013-02-06 17:26 ` [PATCH 6/6] perf, amd: Enable northbridge performance counters on AMD family 15h Jacob Shin
2013-02-07 17:57   ` Jacob Shin
2013-02-07 17:58     ` Stephane Eranian
2013-02-07 19:09     ` Ingo Molnar [this message]
2013-02-08 11:16   ` Stephane Eranian
2013-02-11 16:26     ` Jacob Shin
2013-02-15 20:51       ` Jacob Shin
2013-02-18  8:30   ` [tip:perf/core] perf/x86/amd: " tip-bot for Jacob Shin
2013-02-06 17:31 ` [PATCH V6 0/6] perf, amd: Enable AMD family 15h northbridge counters Jacob Shin
2013-02-08 10:55   ` Stephane Eranian
  -- strict thread matches above, loose matches on Subject: below --
2012-12-05 23:04 [PATCH V4 " Jacob Shin
2012-12-05 23:04 ` [PATCH 6/6] perf, amd: Enable northbridge performance counters on AMD family 15h Jacob Shin

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