From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ben Widawsky <ben@bwidawsk.net>
Subject: Re: [PATCH 07/10] drm/i915: print Gen5+ CPU poison
 interrupts
Date: Sat, 9 Feb 2013 09:30:24 -0800
Message-ID: <20130209093024.000022a8@unknown>
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To: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: intel-gfx@lists.freedesktop.org, Paulo Zanoni <paulo.r.zanoni@intel.com>
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On Fri, 8 Feb 2013 11:42:39 -0800
Jesse Barnes <jbarnes@virtuousgeek.org> wrote:

> On Fri,  8 Feb 2013 17:35:18 -0200
> Paulo Zanoni <przanoni@gmail.com> wrote:
> 
> > From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > 
> > On ILK/SNB all we need to do is to enable the "poison" bit, but on
> > IVB/HSW we need to enable the CPU error interrupt register, which is
> > responsible not only for poison interrupts, but also other things.
> > This includes the "unclaimed register" interrupt, so on the IVB irq
> > handler we now need to: (i) check whether the interrupt was
> > triggered by an unclaimed register and (ii) mask the error
> > interrupt bit so we don't risk generating "unclaimed register"
> > interrupts form inside the interrupt handler.
> > 
> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > ---
> 
> OTOH there's nothing the user can do about it... so we might do a
> WARN_ONCE or something here instead.  But even then, I'm not sure
> there's much *we* can do about these, as they indicate a corruption in
> the communication between the CPU and PCH.
> 

I agree with Jesse. I wouldn't bother with these. Even a WARN_ONCE
isn't helpful since the backtrace wouldn't really be meaningful.

If OTOH, you wanted to save away this information into error state; I
could get behind that.