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diff for duplicates of <201302092223.11796.arnd@arndb.de>

diff --git a/a/1.txt b/N1/1.txt
index da7cd4b..add1aff 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -1,6 +1,6 @@
 On Friday 08 February 2013, Jason Gunthorpe wrote:
 > On Thu, Feb 07, 2013 at 11:25:23PM +0000, Arnd Bergmann wrote:
-> > > link@0 {
+> > > link at 0 {
 > > > reg = <0x800 0 0  0 0>; // Bus 0, Dev 0x10, Fn 0
 > > > interrupt-mask = <0x0 0 0 7>;
 > > > interrupt-map = <0x0000 0 0 1 &mpic 58 // INTA
@@ -35,7 +35,7 @@ the standard says, but it seems they both agree with you in this
 case: http://www.openfirmware.org/1275/practice/imap/imap0_9d.pdf
 defines that "At any level in the interrupt tree, a mapping may
 need to take place between the child interrupt domain and the
-parent’s. This is represented by a new property called 'interrupt-map'".
+parent?s. This is represented by a new property called 'interrupt-map'".
 
 > This matches the design of PCI - if you know how interrupts are hooked
 > up then use that information, otherwise assume the INTx interrupts
@@ -82,7 +82,7 @@ below them.
 > to a PCI-E to PCI bridge, with 2 physical PCI bus slots. The
 > interrupts for the 2 slots are routed to the CPU directly:
 > 
-> link@0 {
+> link at 0 {
 >  reg = </* Bus 0, Dev 0x10, Fn 0 */>; // Root Port bridge
 > 
 >   // Match on INTx (not used since the pci-bridge doesn't create inband INTx)
@@ -92,10 +92,10 @@ below them.
 
 What are these two interrupts in the example then?
 
->  pci_bridge@0 {
+>  pci_bridge at 0 {
 >     reg = </* Bus 1, Dev 0x10, Fn 0 */>; // PCIe to PCI bridge
 
-The device would be "pci@10", right?
+The device would be "pci at 10", right?
 
 >     // Match on the device/slot and INTx pin
 >     interrupt-mask = <0x7f 0 0 7>;
diff --git a/a/content_digest b/N1/content_digest
index cb0f8a5..f1fd6c9 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -1,32 +1,15 @@
  "ref\01359399397-29729-20-git-send-email-thomas.petazzoni@free-electrons.com\0"
  "ref\0201302072325.23483.arnd@arndb.de\0"
  "ref\020130208004414.GA32245@obsidianresearch.com\0"
- "From\0Arnd Bergmann <arnd@arndb.de>\0"
- "Subject\0Re: [PATCH v2 19/27] pci: PCIe driver for Marvell Armada 370/XP systems\0"
+ "From\0arnd@arndb.de (Arnd Bergmann)\0"
+ "Subject\0[PATCH v2 19/27] pci: PCIe driver for Marvell Armada 370/XP systems\0"
  "Date\0Sat, 9 Feb 2013 22:23:11 +0000\0"
- "To\0Jason Gunthorpe <jgunthorpe@obsidianresearch.com>\0"
- "Cc\0Thomas Petazzoni <thomas.petazzoni@free-electrons.com>"
-  Andrew Murray <andrew.murray@arm.com>
-  Bjorn Helgaas <bhelgaas@google.com>
-  linux-pci@vger.kernel.org <linux-pci@vger.kernel.org>
-  linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org>
-  Jason Cooper <jason@lakedaemon.net>
-  Andrew Lunn <andrew@lunn.ch>
-  Gregory Clement <gregory.clement@free-electrons.com>
-  Maen Suleiman <maen@marvell.com>
-  Lior Amsalem <alior@marvell.com>
-  Thierry Reding <thierry.reding@avionic-design.de>
-  Eran Ben-Avi <benavi@marvell.com>
-  Nadav Haklai <nadavh@marvell.com>
-  Shadi Ammouri <shadi@marvell.com>
-  Tawfik Bayouk <tawfik@marvell.com>
-  Stephen Warren <swarren@wwwdotorg.org>
- " Russell King - ARM Linux <linux@arm.linux.org.uk>\0"
+ "To\0linux-arm-kernel@lists.infradead.org\0"
  "\00:1\0"
  "b\0"
  "On Friday 08 February 2013, Jason Gunthorpe wrote:\n"
  "> On Thu, Feb 07, 2013 at 11:25:23PM +0000, Arnd Bergmann wrote:\n"
- "> > > link@0 {\n"
+ "> > > link at 0 {\n"
  "> > > reg = <0x800 0 0  0 0>; // Bus 0, Dev 0x10, Fn 0\n"
  "> > > interrupt-mask = <0x0 0 0 7>;\n"
  "> > > interrupt-map = <0x0000 0 0 1 &mpic 58 // INTA\n"
@@ -61,7 +44,7 @@
  "case: http://www.openfirmware.org/1275/practice/imap/imap0_9d.pdf\n"
  "defines that \"At any level in the interrupt tree, a mapping may\n"
  "need to take place between the child interrupt domain and the\n"
- "parent\342\200\231s. This is represented by a new property called 'interrupt-map'\".\n"
+ "parent?s. This is represented by a new property called 'interrupt-map'\".\n"
  "\n"
  "> This matches the design of PCI - if you know how interrupts are hooked\n"
  "> up then use that information, otherwise assume the INTx interrupts\n"
@@ -108,7 +91,7 @@
  "> to a PCI-E to PCI bridge, with 2 physical PCI bus slots. The\n"
  "> interrupts for the 2 slots are routed to the CPU directly:\n"
  "> \n"
- "> link@0 {\n"
+ "> link at 0 {\n"
  ">  reg = </* Bus 0, Dev 0x10, Fn 0 */>; // Root Port bridge\n"
  "> \n"
  ">   // Match on INTx (not used since the pci-bridge doesn't create inband INTx)\n"
@@ -118,10 +101,10 @@
  "\n"
  "What are these two interrupts in the example then?\n"
  "\n"
- ">  pci_bridge@0 {\n"
+ ">  pci_bridge at 0 {\n"
  ">     reg = </* Bus 1, Dev 0x10, Fn 0 */>; // PCIe to PCI bridge\n"
  "\n"
- "The device would be \"pci@10\", right?\n"
+ "The device would be \"pci at 10\", right?\n"
  "\n"
  ">     // Match on the device/slot and INTx pin\n"
  ">     interrupt-mask = <0x7f 0 0 7>;\n"
@@ -145,4 +128,4 @@
  "\n"
  "\tArnd"
 
-3c8d785fa3278dc426dabe7b3252176086ed547a34d8bf52b6e053e13877a2ef
+2934162102b341e6361635f65ba16196908d4a3c216cc929862d95959f7b133e

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