From: Ralf Baechle <ralf@linux-mips.org>
To: folkert <folkert@vanheusden.com>
Cc: linux-mips@linux-mips.org
Subject: Re: prom start
Date: Sun, 10 Feb 2013 13:56:25 +0100 [thread overview]
Message-ID: <20130210125625.GA32552@linux-mips.org> (raw)
In-Reply-To: <20130206160508.GR2118@belle.intranet.vanheusden.com>
On Wed, Feb 06, 2013 at 05:05:10PM +0100, folkert wrote:
> Is this mailing list also meant for generic mips questions? (if not: any
> suggestions for one that is?)
>
> If so: I'mm experimenting a bit with mips, specifically on SGI hardware
> (Indigo). Now it seems all mips systems have the prom at 0xbfc00000. But
> how does it start? The first 0x3c0 bytes seem to be nonsense. Somewhere
> on the web I found that 0xbfc00884 is the starting point but after
> single stepping 5 instructions, the program counter jumps to 0x00000000
> so I don't think that's the right one either. Also, reading the first 4
> bytes from bfc00000 and using that as a pointer seems to be invalid too:
> 0bf000f0.
> Anyone with insights regarding the booting of the prom on sgi systems?
All MIPS processors start execution at 0xbfc00000 after a hardware reset
or NMI. 0xbfc00884 is not an address that has any specific meaning in
the processor architecture itself. I think it's being used in the GXemul
documentation just for sake of an example.
If your disassembler defaults to like MIPS I / R3000 it won't disassemble
all instructions for the MIPS III R4000 processor. I'd expect some
cache initialization code right at 0xbfc00000 and that could would be
affected.
Ralf
next prev parent reply other threads:[~2013-02-10 12:56 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-02-06 16:05 prom start folkert
2013-02-10 3:54 ` Joshua Kinard
2013-02-10 12:56 ` Ralf Baechle [this message]
2013-02-10 16:43 ` folkert
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