diff for duplicates of <20130212192615.GC1471@obsidianresearch.com> diff --git a/a/1.txt b/N1/1.txt index 8c4400c..76ec79f 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -54,7 +54,7 @@ it's own downstream interrupt layout - and thus is an interrupt domain. > > to a PCI-E to PCI bridge, with 2 physical PCI bus slots. The > > interrupts for the 2 slots are routed to the CPU directly: > > -> > link@0 { +> > link at 0 { > > reg = </* Bus 0, Dev 0x10, Fn 0 */>; // Root Port bridge > > > > // Match on INTx (not used since the pci-bridge doesn't create inband INTx) @@ -64,7 +64,7 @@ it's own downstream interrupt layout - and thus is an interrupt domain. > > What are these two interrupts in the example then? -This shows that the HW block 'link@0' - which is a PCI Express root +This shows that the HW block 'link at 0' - which is a PCI Express root port bridge - accepts inband INTx messages and converts them to CPU interrupts pic 0/1/... @@ -75,10 +75,10 @@ However, the board has a hard-wired PCIe to PCI bridge with PCI slots, and never generates inband INTx. We can then describe that chip via the following stanza in the board specific dts: -> > pci_bridge@0 { +> > pci_bridge at 0 { > > reg = </* Bus 1, Dev 0x10, Fn 0 */>; // PCIe to PCI bridge > -> The device would be "pci@10", right? +> The device would be "pci at 10", right? Probably best to use the hex version of the regs value /* Bus 1, Dev 0x10, Fn 0 */, but nothing inspects that, right? @@ -102,7 +102,7 @@ own interrupt pins and converts those to inband PCIe INTx messages, then the PCB can wire up the PCI bus slots to the bridge's INTx pins according to some pattern and describe that pattern in DT: -pci_bridge@0 { +pci_bridge at 0 { reg = </* Bus 1, Dev 0x10, Fn 0 */>; // PCIe to PCI bridge interrupt-mask = <0xf800 0 0 7>; interrupt-map = <0x00xx 0 0 1 &pci_bridge0 0 0 0 1 // Slot 0 physical INTA to inband INTA @@ -114,7 +114,7 @@ pci_bridge@0 { be OK) Which would be processed as: - - pci_bridge@0 converts out of brand interrupts into in-band + - pci_bridge at 0 converts out of brand interrupts into in-band interrupts according its interrupt-map, and then sends those upstream. - link@0 converts in band interrupts into CPU interrupts according diff --git a/a/content_digest b/N1/content_digest index af35b5d..5b94eb1 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -2,27 +2,10 @@ "ref\0201302072325.23483.arnd@arndb.de\0" "ref\020130208004414.GA32245@obsidianresearch.com\0" "ref\0201302092223.11796.arnd@arndb.de\0" - "From\0Jason Gunthorpe <jgunthorpe@obsidianresearch.com>\0" - "Subject\0Re: [PATCH v2 19/27] pci: PCIe driver for Marvell Armada 370/XP systems\0" + "From\0jgunthorpe@obsidianresearch.com (Jason Gunthorpe)\0" + "Subject\0[PATCH v2 19/27] pci: PCIe driver for Marvell Armada 370/XP systems\0" "Date\0Tue, 12 Feb 2013 12:26:15 -0700\0" - "To\0Arnd Bergmann <arnd@arndb.de>\0" - "Cc\0Thomas Petazzoni <thomas.petazzoni@free-electrons.com>" - Andrew Murray <andrew.murray@arm.com> - Bjorn Helgaas <bhelgaas@google.com> - linux-pci@vger.kernel.org <linux-pci@vger.kernel.org> - linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org> - Jason Cooper <jason@lakedaemon.net> - Andrew Lunn <andrew@lunn.ch> - Gregory Clement <gregory.clement@free-electrons.com> - Maen Suleiman <maen@marvell.com> - Lior Amsalem <alior@marvell.com> - Thierry Reding <thierry.reding@avionic-design.de> - Eran Ben-Avi <benavi@marvell.com> - Nadav Haklai <nadavh@marvell.com> - Shadi Ammouri <shadi@marvell.com> - Tawfik Bayouk <tawfik@marvell.com> - Stephen Warren <swarren@wwwdotorg.org> - " Russell King - ARM Linux <linux@arm.linux.org.uk>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "On Sat, Feb 09, 2013 at 10:23:11PM +0000, Arnd Bergmann wrote:\n" @@ -81,7 +64,7 @@ "> > to a PCI-E to PCI bridge, with 2 physical PCI bus slots. The\n" "> > interrupts for the 2 slots are routed to the CPU directly:\n" "> > \n" - "> > link@0 {\n" + "> > link at 0 {\n" "> > reg = </* Bus 0, Dev 0x10, Fn 0 */>; // Root Port bridge\n" "> > \n" "> > // Match on INTx (not used since the pci-bridge doesn't create inband INTx)\n" @@ -91,7 +74,7 @@ "> \n" "> What are these two interrupts in the example then?\n" "\n" - "This shows that the HW block 'link@0' - which is a PCI Express root\n" + "This shows that the HW block 'link at 0' - which is a PCI Express root\n" "port bridge - accepts inband INTx messages and converts them to CPU\n" "interrupts pic 0/1/...\n" "\n" @@ -102,10 +85,10 @@ "and never generates inband INTx. We can then describe that chip via\n" "the following stanza in the board specific dts:\n" "\n" - "> > pci_bridge@0 {\n" + "> > pci_bridge at 0 {\n" "> > reg = </* Bus 1, Dev 0x10, Fn 0 */>; // PCIe to PCI bridge\n" "> \n" - "> The device would be \"pci@10\", right?\n" + "> The device would be \"pci at 10\", right?\n" "\n" "Probably best to use the hex version of the regs value /* Bus 1, Dev\n" "0x10, Fn 0 */, but nothing inspects that, right?\n" @@ -129,7 +112,7 @@ "then the PCB can wire up the PCI bus slots to the bridge's INTx pins\n" "according to some pattern and describe that pattern in DT:\n" "\n" - "pci_bridge@0 {\n" + "pci_bridge at 0 {\n" " reg = </* Bus 1, Dev 0x10, Fn 0 */>; // PCIe to PCI bridge\n" " interrupt-mask = <0xf800 0 0 7>;\n" " interrupt-map = <0x00xx 0 0 1 &pci_bridge0 0 0 0 1 // Slot 0 physical INTA to inband INTA\n" @@ -141,7 +124,7 @@ "be OK)\n" "\n" "Which would be processed as:\n" - " - pci_bridge@0 converts out of brand interrupts into in-band\n" + " - pci_bridge at 0 converts out of brand interrupts into in-band\n" " interrupts according its interrupt-map, and then sends those\n" " upstream.\n" " - link@0 converts in band interrupts into CPU interrupts according\n" @@ -159,4 +142,4 @@ "Cheers,\n" Jason -cd188c6f792814ae5140c71b73dd8ae3492bba32628deeb351a13e983b4d7841 +b390294a9ce2967c2701714ecdc7d51fbdcc62487acbac4d9a74ee8eac2aa8be
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