From mboxrd@z Thu Jan  1 00:00:00 1970
From: Daniel Vetter <daniel@ffwll.ch>
Subject: Re: [PATCH v2] drm/i915: Fix PIPE_CONTROL DW/QW write
 through global GTT on IVB+
Date: Fri, 15 Feb 2013 11:10:17 +0100
Message-ID: <20130215101017.GC5813@phenom.ffwll.local>
References: <1360871631-20578-1-git-send-email-ville.syrjala@linux.intel.com>
	<20130214224642.GA26753@bwidawsk.net>
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To: Ben Widawsky <ben@bwidawsk.net>
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On Thu, Feb 14, 2013 at 02:46:44PM -0800, Ben Widawsky wrote:
> On Thu, Feb 14, 2013 at 09:53:51PM +0200, ville.syrjala@linux.intel.com w=
rote:
> > From: Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.com>
> > =

> > The bit controlling whether PIPE_CONTROL DW/QW write targets
> > the global GTT or PPGTT moved moved from DW 2 bit 2 to
> > DW 1 bit 24 on IVB.
> > =

> > I verified on IVB that the fix is in fact effective. Without the fix
> > none of the scratch writes actually landed in the pipe control page.
> > With the fix the writes show up correctly.
> > =

> > v2: move PIPE_CONTROL_GLOBAL_GTT_IVB setup to where other flags are set
> > =

> > Signed-off-by: Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.com>
> Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Queued for -next, thanks for the patch.
-Daniel
-- =

Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch