From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
Subject: Re: [PATCH v2] drm/i915: Fix PIPE_CONTROL DW/QW write
 through global GTT on IVB+
Date: Wed, 20 Feb 2013 16:32:50 +0200
Message-ID: <20130220143250.GB4469@intel.com>
References: <1360871631-20578-1-git-send-email-ville.syrjala@linux.intel.com>
	<20130214224642.GA26753@bwidawsk.net>
	<20130219235915.GA1701@bwidawsk.net>
Mime-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
Return-path: <intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org>
Received: from mga01.intel.com (mga01.intel.com [192.55.52.88])
	by gabe.freedesktop.org (Postfix) with ESMTP id 7CE11E675E
	for <intel-gfx@lists.freedesktop.org>;
	Wed, 20 Feb 2013 06:33:16 -0800 (PST)
Content-Disposition: inline
In-Reply-To: <20130219235915.GA1701@bwidawsk.net>
List-Unsubscribe: <http://lists.freedesktop.org/mailman/options/intel-gfx>,
	<mailto:intel-gfx-request@lists.freedesktop.org?subject=unsubscribe>
List-Archive: <http://lists.freedesktop.org/archives/intel-gfx>
List-Post: <mailto:intel-gfx@lists.freedesktop.org>
List-Help: <mailto:intel-gfx-request@lists.freedesktop.org?subject=help>
List-Subscribe: <http://lists.freedesktop.org/mailman/listinfo/intel-gfx>,
	<mailto:intel-gfx-request@lists.freedesktop.org?subject=subscribe>
Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org
Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org
To: Ben Widawsky <ben@bwidawsk.net>
Cc: intel-gfx@lists.freedesktop.org
List-Id: intel-gfx@lists.freedesktop.org

On Tue, Feb 19, 2013 at 03:59:16PM -0800, Ben Widawsky wrote:
> On Thu, Feb 14, 2013 at 02:46:44PM -0800, Ben Widawsky wrote:
> > On Thu, Feb 14, 2013 at 09:53:51PM +0200, ville.syrjala@linux.intel.com=
 wrote:
> > > From: Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.com>
> > > =

> > > The bit controlling whether PIPE_CONTROL DW/QW write targets
> > > the global GTT or PPGTT moved moved from DW 2 bit 2 to
> > > DW 1 bit 24 on IVB.
> > > =

> > > I verified on IVB that the fix is in fact effective. Without the fix
> > > none of the scratch writes actually landed in the pipe control page.
> > > With the fix the writes show up correctly.
> > > =

> > > v2: move PIPE_CONTROL_GLOBAL_GTT_IVB setup to where other flags are s=
et
> > > =

> > > Signed-off-by: Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.com>
> > Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
> > [snip]
> =

> Reading the bspec again... do we want to set bit 21?

I don't think we want to do that. The scratch address we're using here
is a proper GTT address, not an index into the HWS page.

I have no idea why we're not using the HSW page here as well. I couldn't
dig out any reason from the commit logs either. Anyone?

-- =

Ville Syrj=E4l=E4
Intel OTC