Re: [PATCH] perf, x86: add Intel IvyBridge event scheduling constraints

[Andi Kleen <ak@linux.intel.com>]

On Wed, Feb 20, 2013 at 11:15:12AM +0100, Stephane Eranian wrote:
> Intel IvyBridge processor has different constraints compared
> to SandyBridge. Therefore it needs its own contraint table.
> This patch adds the constraint table. Without this patch,
> the events listed in the patch may not be scheduled correctly
> and bogus counts may be collected.

Thanks. I ran into this problem too and was about to write 
a similar patch.

> +	INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
> +	INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
> +	INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
> +	INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
> +	INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */


Except for LDM_PENDING the CYCLE_ACTIVITY events have been also added to Sandy Bridge.
So it should be also added there.

In fact I think you can still share the table because it would just add some 
non existent events to Sandy Bridge, which is a noop.

-Andi