From mboxrd@z Thu Jan  1 00:00:00 1970
From: Daniel Vetter <daniel@ffwll.ch>
Subject: Re: [PATCH] drm/i915: Kill pipestat[] cache
Date: Thu, 21 Feb 2013 14:01:32 +0100
Message-ID: <20130221130132.GG5813@phenom.ffwll.local>
References: <1361387778-18037-1-git-send-email-ville.syrjala@linux.intel.com>
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To: Jani Nikula <jani.nikula@linux.intel.com>
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On Thu, Feb 21, 2013 at 10:34:54AM +0200, Jani Nikula wrote:
> On Wed, 20 Feb 2013, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.com>
> >
> > Caching the PIPESTAT enable bits has been deemed pointless. Just
> > read them from the register itself.
> =

> Reviewed-by: Jani Nikula <jani.nikula@intel.com>

Queued for -next, thanks for the patch.
-Daniel
-- =

Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch