From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 6/8] drm/i915: Enable/Disable PSR Date: Tue, 26 Feb 2013 14:48:33 +0200 Message-ID: <20130226124833.GS4469@intel.com> References: <1361832922-19801-1-git-send-email-rodrigo.vivi@gmail.com> <1361832922-19801-7-git-send-email-rodrigo.vivi@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Content-Disposition: inline In-Reply-To: <1361832922-19801-7-git-send-email-rodrigo.vivi@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: dri-devel-bounces+sf-dri-devel=m.gmane.org@lists.freedesktop.org Errors-To: dri-devel-bounces+sf-dri-devel=m.gmane.org@lists.freedesktop.org To: Rodrigo Vivi Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org On Mon, Feb 25, 2013 at 07:55:20PM -0300, Rodrigo Vivi wrote: > Adding Enable and Disable PSR functionalities. This includes setting the > PSR configuration over AUX, sending SDP VSC DIP over the eDP PIPE config, > enabling PSR in the sink via DPCD register and finally enabling PSR on > the host. > = > This patch is heavily based on initial PSR code by Sateesh Kavuri and > Kumar Shobhit but in a different implementation. > = > Credits-by: Sateesh Kavuri > Credits-by: Shobhit Kumar > Signed-off-by: Rodrigo Vivi > --- > drivers/gpu/drm/i915/i915_reg.h | 40 +++++++++ > drivers/gpu/drm/i915/intel_dp.c | 183 +++++++++++++++++++++++++++++++++= ++++++ > drivers/gpu/drm/i915/intel_drv.h | 3 + > 3 files changed, 226 insertions(+) > = > +void intel_edp_write_vsc_psr(struct intel_dp* intel_dp, > + struct edp_vsc_psr *vsc_psr) > +{ > + struct drm_device *dev =3D intel_dp_to_dev(intel_dp); > + struct drm_i915_private *dev_priv =3D dev->dev_private; > + struct intel_crtc *intel_crtc =3D to_intel_crtc(intel_dp_to_crtc(intel= _dp)); > + u32 ctl_reg =3D HSW_TVIDEO_DIP_CTL(intel_crtc->cpu_transcoder); > + u32 data_reg =3D HSW_TVIDEO_DIP_VSC_DATA(intel_crtc->cpu_transcoder); > + uint32_t *data =3D (uint32_t *)vsc_psr; > + unsigned int i; > + u32 val =3D I915_READ(ctl_reg); > + > + if (data_reg =3D=3D 0) > + return; > + > + /* As per eDP spec, wait for vblank to send SDP VSC packet */ > + intel_wait_for_vblank(dev, intel_crtc->pipe); > + > + mmiowb(); I was curious about these mmiowb()s and apparently they were added to all infoframe writes "just in case". But AFAICS on x86 mmiowb() ends up as a compiler barrier, so this stuff seems to be a nop. And if these writes can get reordered somewhere, why not everything else too? I'm sure we have places where we write a bunch of registers, and the final write enables something which requires the earlier writes to have landed beforehand. -- = Ville Syrj=E4l=E4 Intel OTC