From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [Intel-gfx] [PATCH 0/8] Enable eDP PSR functionality at HSW - v3 Date: Thu, 28 Feb 2013 20:02:18 +0200 Message-ID: <20130228180218.GA4469@intel.com> References: <1361832922-19801-1-git-send-email-rodrigo.vivi@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Content-Disposition: inline In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: dri-devel-bounces+sf-dri-devel=m.gmane.org@lists.freedesktop.org Errors-To: dri-devel-bounces+sf-dri-devel=m.gmane.org@lists.freedesktop.org To: Paulo Zanoni Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org On Thu, Feb 28, 2013 at 02:52:32PM -0300, Paulo Zanoni wrote: > Hi > = > 2013/2/25 Rodrigo Vivi : > > PSR is an eDP feature that allows power saving even with static image a= t eDP screen. > > > > v3: Accepted many suggestions that I received at v2 review, fixing, cle= aning and improving the code. > > > > v2: Main differences in this v2: > > - Created vbt struct to get i915 dev_priv more organized and to avoid a= dding more stuff into it. > > - migrated hsw macros to use transcoder instead of pipes than I could a= ddress eDP > > - remove patch that was only adding edp psr registers and added them on= demand > > > > v1: > > Shobit Kumar has implemented this patch series some time ago, but had n= o eDP panel with PSR capability to test them. > > > > I could test and verify that this series fully identify PSR capability = and enables it at HSW. > > I also verified that it saves from 0.5-1W but only when in blank screen= . It seems it is not really entering in sleeping mode with static image at = eDP screen yet. > = > What do you mean with "blank screen"? It seems we disable PSR before > blanking the screen, so the 0.5-1W saving could be from the backlight. > Did you try masking more bits on the SRD_DEBUG register to see if it > enters PSR more easily? The first test I'd try would be to set 1 to > all those mask regs and see what happens (maybe we'll enter PSR and > never ever leave it again?). One thing I'm wondering if we can even enable PSR w/o implementing the FBC tracking bits. I mean what happens if someone renders to the front buffer while PSR is active? -- = Ville Syrj=E4l=E4 Intel OTC