From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 07/28] drm/i915: implement WaForceL3Serialization on VLV and IVB Date: Fri, 1 Mar 2013 23:43:25 +0200 Message-ID: <20130301214325.GD4469@intel.com> References: <1362172471-7643-1-git-send-email-jbarnes@virtuousgeek.org> <1362172471-7643-8-git-send-email-jbarnes@virtuousgeek.org> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 31A48E6253 for ; Fri, 1 Mar 2013 13:43:30 -0800 (PST) Content-Disposition: inline In-Reply-To: <1362172471-7643-8-git-send-email-jbarnes@virtuousgeek.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Jesse Barnes Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Fri, Mar 01, 2013 at 01:14:10PM -0800, Jesse Barnes wrote: > References: https://bugs.freedesktop.org/show_bug.cgi?id=3D50250 > Signed-off-by: Jesse Barnes > --- > drivers/gpu/drm/i915/i915_reg.h | 3 +++ > drivers/gpu/drm/i915/intel_pm.c | 4 ++++ > 2 files changed, 7 insertions(+) > = > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_= reg.h > index 766518b..09b9072 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -3583,6 +3583,9 @@ > #define GEN7_L3SQCREG4 0xb034 > #define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27) > = > +#define GEN7_L3SQCREG4 0xb034 > +#define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27) > + > /* WaCatErrorRejectionIssue */ > #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030 > #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11) > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel= _pm.c > index 61fee7f..0f1adc8 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3830,6 +3830,10 @@ static void ivybridge_init_clock_gating(struct drm= _device *dev) > I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & > ~L3SQ_URB_READ_CAM_MATCH_DISABLE); > = > + /* WaForceL3Serialization */ > + I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & > + ~L3SQ_URB_READ_CAM_MATCH_DISABLE); I suspect doing it twice won't serialize things any further ;) Actually it seems we're already clearing the bit twice. So this is the third one you're adding. > + > /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock > * gating disable must be set. Failure to set it results in > * flickering pixels due to Z write ordering failures after > -- = > 1.7.9.5 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC