From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 08/28] drm/i915: implement WaGTEnableMiFlush on VLV Date: Fri, 1 Mar 2013 23:47:01 +0200 Message-ID: <20130301214701.GF4469@intel.com> References: <1362172471-7643-1-git-send-email-jbarnes@virtuousgeek.org> <1362172471-7643-9-git-send-email-jbarnes@virtuousgeek.org> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 82CD8E65B4 for ; Fri, 1 Mar 2013 13:47:04 -0800 (PST) Content-Disposition: inline In-Reply-To: <1362172471-7643-9-git-send-email-jbarnes@virtuousgeek.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Jesse Barnes Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Fri, Mar 01, 2013 at 01:14:11PM -0800, Jesse Barnes wrote: > We don't generally use MI_FLUSH these days, but this bit may affect > other flushing logic, so set it to be safe. My earlier question stands. Why are we doing this only for VLV, when the WA applies to everything since SNB? > = > Signed-off-by: Jesse Barnes > --- > drivers/gpu/drm/i915/intel_ringbuffer.c | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > = > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i9= 15/intel_ringbuffer.c > index 1d5d613..e82b994 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -524,10 +524,14 @@ static int init_render_ring(struct intel_ring_buffe= r *ring) > I915_WRITE(GFX_MODE, > _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS)); > = > - if (IS_GEN7(dev)) > + if (IS_GEN7(dev)) { > I915_WRITE(GFX_MODE_GEN7, > _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) | > _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); > + if (IS_VALLEYVIEW(dev)) > + I915_WRITE(MI_MODE, I915_READ(MI_MODE) | > + _MASKED_BIT_ENABLE(MI_FLUSH_ENABLE)); > + } > = > if (INTEL_INFO(dev)->gen >=3D 5) { > ret =3D init_pipe_control(ring); > -- = > 1.7.9.5 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC