From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH] drm/i915: Turn off hsync and vsync on ADPA when disabling crt Date: Tue, 5 Mar 2013 15:45:30 +0200 Message-ID: <20130305134530.GU4469@intel.com> References: <1362489888-32651-1-git-send-email-patrik.r.jakobsson@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 5577BE63A4 for ; Tue, 5 Mar 2013 05:45:51 -0800 (PST) Content-Disposition: inline In-Reply-To: <1362489888-32651-1-git-send-email-patrik.r.jakobsson@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Patrik Jakobsson Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Tue, Mar 05, 2013 at 02:24:48PM +0100, Patrik Jakobsson wrote: > According to PRM we need to disable hsync and vsync even though ADPA is > disabled. The previous code did infact do the opposite so we fix it. > = > Signed-off-by: Patrik Jakobsson > > --- > drivers/gpu/drm/i915/intel_crt.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > = > diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/inte= l_crt.c > index 969d08c..32a3693 100644 > --- a/drivers/gpu/drm/i915/intel_crt.c > +++ b/drivers/gpu/drm/i915/intel_crt.c > @@ -88,7 +88,7 @@ static void intel_disable_crt(struct intel_encoder *enc= oder) > u32 temp; > = > temp =3D I915_READ(crt->adpa_reg); > - temp &=3D ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE); > + temp |=3D ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; Accroding to the docs these bits don't exist on PCH platforms. intel_crt_dpms() already has a check for this, so I suppose intel_disable_crt() should have one too. Also I noticed that we seem to have the hsync and vsync disable bits reversed. At least that's what the docs are telling me. > > temp &=3D ~ADPA_DAC_ENABLE; > I915_WRITE(crt->adpa_reg, temp); > } > -- = > 1.7.10.4 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC