From mboxrd@z Thu Jan 1 00:00:00 1970 From: Arnd Bergmann Subject: Re: [PATCH v2 1/4] spi/davinci: add DT binding documentation Date: Tue, 5 Mar 2013 19:32:41 +0000 Message-ID: <201303051932.41327.arnd@arndb.de> References: <1362401955-9616-1-git-send-email-prakash.pm@ti.com> <6918845.dALXSKksQd@wuerfel> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Cc: "davinci-linux-open-source-VycZQUHpC/PFrsHnngEfi1aTQe2KTcn/@public.gmane.org" , "linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org" , "linux-doc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org" , "Nori, Sekhar" , "rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org" , "Karicheri, Muralidharan" , "rob-VoJi6FS/r0vR7s880joybQ@public.gmane.org" , "spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org" , "hs-ynQEQJNshbs@public.gmane.org" , "linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" To: "Manjunathappa, Prakash" Return-path: In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: spi-devel-general-bounces-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org List-Id: linux-spi.vger.kernel.org On Tuesday 05 March 2013, Manjunathappa, Prakash wrote: > On Mon, Mar 04, 2013 at 21:59:16, Arnd Bergmann wrote: > > On Monday 04 March 2013 18:29:12 Manjunathappa, Prakash wrote: > > > +- reg: Offset and length of SPI controller register space > > > +- num-cs: Number of chip selects > > > +- ti,davinci-spi-intr-line: interrupt line used to connect the SPI > > > + IP to the interrupt controller withn the SoC. Possible values > > > + are 0 and 1. Manual says one of the two possible interrupt > > > + lines can be tied to the interrupt controller. Set this > > > + based on a specifc SoC configuration. > > > +- interrupts: interrupt number offset at the irq parent > > > > I would not call this an "offset". It is an interrupt descriptor > > which may be something other than a simple number. > > > > I am planning to drop from this documentation as it is common property. I think it makese sense to document the fact that there should be exactly one interrupt listed in the interrupts property, especially since the hardware has two outputs. Arnd ------------------------------------------------------------------------------ Everyone hates slow websites. So do we. Make your web apps faster with AppDynamics Download AppDynamics Lite for free today: http://p.sf.net/sfu/appdyn_d2d_feb From mboxrd@z Thu Jan 1 00:00:00 1970 From: arnd@arndb.de (Arnd Bergmann) Date: Tue, 5 Mar 2013 19:32:41 +0000 Subject: [PATCH v2 1/4] spi/davinci: add DT binding documentation In-Reply-To: References: <1362401955-9616-1-git-send-email-prakash.pm@ti.com> <6918845.dALXSKksQd@wuerfel> Message-ID: <201303051932.41327.arnd@arndb.de> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Tuesday 05 March 2013, Manjunathappa, Prakash wrote: > On Mon, Mar 04, 2013 at 21:59:16, Arnd Bergmann wrote: > > On Monday 04 March 2013 18:29:12 Manjunathappa, Prakash wrote: > > > +- reg: Offset and length of SPI controller register space > > > +- num-cs: Number of chip selects > > > +- ti,davinci-spi-intr-line: interrupt line used to connect the SPI > > > + IP to the interrupt controller withn the SoC. Possible values > > > + are 0 and 1. Manual says one of the two possible interrupt > > > + lines can be tied to the interrupt controller. Set this > > > + based on a specifc SoC configuration. > > > +- interrupts: interrupt number offset at the irq parent > > > > I would not call this an "offset". It is an interrupt descriptor > > which may be something other than a simple number. > > > > I am planning to drop from this documentation as it is common property. I think it makese sense to document the fact that there should be exactly one interrupt listed in the interrupts property, especially since the hardware has two outputs. Arnd