From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 07/26] drm/i915: implement WaDisablePSDDualDispatchEnable on VLV Date: Wed, 6 Mar 2013 20:20:21 +0200 Message-ID: <20130306182021.GG4469@intel.com> References: <1362175722-9281-1-git-send-email-jbarnes@virtuousgeek.org> <1362175722-9281-7-git-send-email-jbarnes@virtuousgeek.org> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 1B3F8E67CC for ; Wed, 6 Mar 2013 10:20:25 -0800 (PST) Content-Disposition: inline In-Reply-To: <1362175722-9281-7-git-send-email-jbarnes@virtuousgeek.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Jesse Barnes Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Fri, Mar 01, 2013 at 02:08:23PM -0800, Jesse Barnes wrote: > Can prevent a hang when we get to tessellation. > = > Signed-off-by: Jesse Barnes > --- > drivers/gpu/drm/i915/intel_pm.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > = > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel= _pm.c > index 61fee7f..59ea12a 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3899,8 +3899,10 @@ static void valleyview_init_clock_gating(struct dr= m_device *dev) > CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | > CHICKEN3_DGMG_DONE_FIX_DISABLE); > = > + /* WaDisablePSDDualDispatchEnable */ > I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, > - _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); > + _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP | > + GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); The comment added matches what we already did. But the thread dep stuff seems to be something else. It seems to match the default value anyway, so shouldn't be needed AFAICS. > = > /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */ > I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, > -- = > 1.7.9.5 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC