From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 25/26] drm/i915/dp: don't use ILK paths on VLV Date: Fri, 8 Mar 2013 16:57:26 +0200 Message-ID: <20130308145726.GC4469@intel.com> References: <1362175722-9281-1-git-send-email-jbarnes@virtuousgeek.org> <1362175722-9281-25-git-send-email-jbarnes@virtuousgeek.org> <874ngmugjc.fsf@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id E14D3E5D02 for ; Fri, 8 Mar 2013 06:57:29 -0800 (PST) Content-Disposition: inline In-Reply-To: <874ngmugjc.fsf@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Jani Nikula Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Fri, Mar 08, 2013 at 04:12:23PM +0200, Jani Nikula wrote: > On Sat, 02 Mar 2013, Jesse Barnes wrote: > > Fix up a couple of places where we messed with PCH bits on VLV. > = > I think there's at least a few more spots that need && !IS_VALLEYVIEW(): > = > --- > } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) { > if (!HAS_PCH_SPLIT(dev)) > intel_dp->DP |=3D intel_dp->color_range; The color_range stuff needs to be tested on real HW. IIRC the spec shows color range bits in both PIPECONF and port register. We need to to find out which one actually works. > --- > if (is_cpu_edp(intel_dp)) { > /* don't miss out required setting for eDP */ > if (adjusted_mode->clock < 200000) > intel_dp->DP |=3D DP_PLL_FREQ_160MHZ; > else > intel_dp->DP |=3D DP_PLL_FREQ_270MHZ; > } > --- > = > BR, > Jani. > = > = > > > > Signed-off-by: Jesse Barnes > > --- > > drivers/gpu/drm/i915/intel_dp.c | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/int= el_dp.c > > index 03340fd..05e1000 100644 > > --- a/drivers/gpu/drm/i915/intel_dp.c > > +++ b/drivers/gpu/drm/i915/intel_dp.c > > @@ -976,7 +976,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, stru= ct drm_display_mode *mode, > > intel_dp->DP |=3D DP_LINK_TRAIN_OFF_CPT; > > } > > = > > - if (is_cpu_edp(intel_dp)) > > + if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) > > ironlake_set_pll_edp(crtc, adjusted_mode->clock); > > } > > = > > @@ -1373,7 +1373,7 @@ static bool intel_dp_get_hw_state(struct intel_en= coder *encoder, > > if (!(tmp & DP_PORT_EN)) > > return false; > > = > > - if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) { > > + if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { > > *pipe =3D PORT_TO_PIPE_CPT(tmp); > > } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) { > > *pipe =3D PORT_TO_PIPE(tmp); > > -- = > > 1.7.9.5 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC