From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 17/20] drm/i915: don't use plane pipe select on VLV Date: Tue, 19 Mar 2013 13:59:57 +0200 Message-ID: <20130319115957.GK4469@intel.com> References: <1362768363-3710-1-git-send-email-jbarnes@virtuousgeek.org> <1362768363-3710-17-git-send-email-jbarnes@virtuousgeek.org> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 783BCE5C91 for ; Tue, 19 Mar 2013 05:00:00 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1362768363-3710-17-git-send-email-jbarnes@virtuousgeek.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Jesse Barnes Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Fri, Mar 08, 2013 at 10:46:00AM -0800, Jesse Barnes wrote: > Planes are fixed to pipes in VLV. > = > Signed-off-by: Jesse Barnes Reviewed-by: Ville Syrj=E4l=E4 > --- > drivers/gpu/drm/i915/intel_display.c | 12 +++++++----- > 1 file changed, 7 insertions(+), 5 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/= intel_display.c > index f1d6404..5e338c6 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -1272,7 +1272,7 @@ static void assert_planes_disabled(struct drm_i915_= private *dev_priv, > int cur_pipe; > = > /* Planes are fixed to pipes on ILK+ */ > - if (HAS_PCH_SPLIT(dev_priv->dev)) { > + if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) { > reg =3D DSPCNTR(pipe); > val =3D I915_READ(reg); > WARN((val & DISPLAY_PLANE_ENABLE), > @@ -4872,10 +4872,12 @@ static int i9xx_crtc_mode_set(struct drm_crtc *cr= tc, > /* Set up the display plane register */ > dspcntr =3D DISPPLANE_GAMMA_ENABLE; > = > - if (pipe =3D=3D 0) > - dspcntr &=3D ~DISPPLANE_SEL_PIPE_MASK; > - else > - dspcntr |=3D DISPPLANE_SEL_PIPE_B; > + if (!IS_VALLEYVIEW(dev)) { > + if (pipe =3D=3D 0) > + dspcntr &=3D ~DISPPLANE_SEL_PIPE_MASK; > + else > + dspcntr |=3D DISPPLANE_SEL_PIPE_B; > + } > = > if (pipe =3D=3D 0 && INTEL_INFO(dev)->gen < 4) { > /* Enable pixel doubling when the dot clock is > 90% of the (display) > -- = > 1.7.10.4 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC