Re: [PATCH v2 3/5] ARM: zynq: add clk support for zynq7000

[Josh Cartwright <joshc@eso.teric.us>]

On Tue, Mar 19, 2013 at 02:35:33PM +0100, Steffen Trumtrar wrote:
> On Tue, Mar 19, 2013 at 08:29:54AM -0500, Josh Cartwright wrote:
> > On Tue, Mar 19, 2013 at 10:21:58AM +0100, Steffen Trumtrar wrote:
> > > This adds support for the clocktree on zynq7000 SoCs.
> > > The patch is based on clocks.c from the larger patch
> > > 	ARM: zynq: add suppport for Zynq 7000 SoC
> > > by Josh Cartwright.
> > > 
> > > The driver in that patch is converted to a platform_driver and code to
> > > enable plls was added.
> > > 
> > > Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
> > > ---
> > [..]
> > > +
> > > +static int zynq_clock_probe(struct device_d *dev)
> > > +{
> > > +	void __iomem *slcr_base;
> > > +	unsigned long ps_clk_rate = 33333330;
> > 
> > My version of the patchset had this ^ configurable, since it's possible
> > a different osc could be used on the board.  Any reason why you've
> > hardcoded this instead?
> > 
> 
> Hm, not really any good reason. But the plan is to get this from the
> devicetree instead. I didn't get around to actually doing that.
> Do your boards have another osc or would a hardcoded value suffice for
> the moment?

I agree that we should be leveraging the device tree here, so maybe it's
worth dropping until we get sorted out.  I'm fine with a hardcoded value
for now.

   Josh

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