[PATCH 01/10] [v2] drm/i915: Move num_pipes to intel info

[PATCH 01/10] [v2] drm/i915: Move num_pipes to intel info

[Ben Widawsky]

Requested by Daniel.

v2: Fix incorrect num_pipe settings. (Chris)

Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_dma.c      |  9 +------
 drivers/gpu/drm/i915/i915_drv.c      | 48 ++++++++++++++++++------------------
 drivers/gpu/drm/i915/i915_drv.h      |  4 +--
 drivers/gpu/drm/i915/i915_irq.c      |  3 +--
 drivers/gpu/drm/i915/intel_display.c | 19 +++++++-------
 drivers/gpu/drm/i915/intel_fb.c      |  2 +-
 drivers/gpu/drm/i915/intel_panel.c   |  2 +-
 7 files changed, 40 insertions(+), 47 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index e16099b..ebcfe2e 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1630,14 +1630,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 	mutex_init(&dev_priv->rps.hw_lock);
 	mutex_init(&dev_priv->modeset_restore_lock);
 
-	if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
-		dev_priv->num_pipe = 3;
-	else if (IS_MOBILE(dev) || !IS_GEN2(dev))
-		dev_priv->num_pipe = 2;
-	else
-		dev_priv->num_pipe = 1;
-
-	ret = drm_vblank_init(dev, dev_priv->num_pipe);
+	ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
 	if (ret)
 		goto out_gem_unload;
 
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 1ebed96..8ff83e9 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -136,74 +136,74 @@ extern int intel_agp_enabled;
 	.driver_data = (unsigned long) info }
 
 static const struct intel_device_info intel_i830_info = {
-	.gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
+	.gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 	.has_overlay = 1, .overlay_needs_physical = 1,
 };
 
 static const struct intel_device_info intel_845g_info = {
-	.gen = 2,
+	.gen = 2, .num_pipes = 1,
 	.has_overlay = 1, .overlay_needs_physical = 1,
 };
 
 static const struct intel_device_info intel_i85x_info = {
-	.gen = 2, .is_i85x = 1, .is_mobile = 1,
+	.gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
 	.cursor_needs_physical = 1,
 	.has_overlay = 1, .overlay_needs_physical = 1,
 };
 
 static const struct intel_device_info intel_i865g_info = {
-	.gen = 2,
+	.gen = 2, .num_pipes = 1,
 	.has_overlay = 1, .overlay_needs_physical = 1,
 };
 
 static const struct intel_device_info intel_i915g_info = {
-	.gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
+	.gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 	.has_overlay = 1, .overlay_needs_physical = 1,
 };
 static const struct intel_device_info intel_i915gm_info = {
-	.gen = 3, .is_mobile = 1,
+	.gen = 3, .is_mobile = 1, .num_pipes = 2,
 	.cursor_needs_physical = 1,
 	.has_overlay = 1, .overlay_needs_physical = 1,
 	.supports_tv = 1,
 };
 static const struct intel_device_info intel_i945g_info = {
-	.gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
+	.gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 	.has_overlay = 1, .overlay_needs_physical = 1,
 };
 static const struct intel_device_info intel_i945gm_info = {
-	.gen = 3, .is_i945gm = 1, .is_mobile = 1,
+	.gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
 	.has_hotplug = 1, .cursor_needs_physical = 1,
 	.has_overlay = 1, .overlay_needs_physical = 1,
 	.supports_tv = 1,
 };
 
 static const struct intel_device_info intel_i965g_info = {
-	.gen = 4, .is_broadwater = 1,
+	.gen = 4, .is_broadwater = 1, .num_pipes = 2,
 	.has_hotplug = 1,
 	.has_overlay = 1,
 };
 
 static const struct intel_device_info intel_i965gm_info = {
-	.gen = 4, .is_crestline = 1,
+	.gen = 4, .is_crestline = 1, .num_pipes = 2,
 	.is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 	.has_overlay = 1,
 	.supports_tv = 1,
 };
 
 static const struct intel_device_info intel_g33_info = {
-	.gen = 3, .is_g33 = 1,
+	.gen = 3, .is_g33 = 1, .num_pipes = 2,
 	.need_gfx_hws = 1, .has_hotplug = 1,
 	.has_overlay = 1,
 };
 
 static const struct intel_device_info intel_g45_info = {
-	.gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
+	.gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
 	.has_pipe_cxsr = 1, .has_hotplug = 1,
 	.has_bsd_ring = 1,
 };
 
 static const struct intel_device_info intel_gm45_info = {
-	.gen = 4, .is_g4x = 1,
+	.gen = 4, .is_g4x = 1, .num_pipes = 2,
 	.is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 	.has_pipe_cxsr = 1, .has_hotplug = 1,
 	.supports_tv = 1,
@@ -211,26 +211,26 @@ static const struct intel_device_info intel_gm45_info = {
 };
 
 static const struct intel_device_info intel_pineview_info = {
-	.gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
+	.gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
 	.need_gfx_hws = 1, .has_hotplug = 1,
 	.has_overlay = 1,
 };
 
 static const struct intel_device_info intel_ironlake_d_info = {
-	.gen = 5,
+	.gen = 5, .num_pipes = 2,
 	.need_gfx_hws = 1, .has_hotplug = 1,
 	.has_bsd_ring = 1,
 };
 
 static const struct intel_device_info intel_ironlake_m_info = {
-	.gen = 5, .is_mobile = 1,
+	.gen = 5, .is_mobile = 1, .num_pipes = 2,
 	.need_gfx_hws = 1, .has_hotplug = 1,
 	.has_fbc = 1,
 	.has_bsd_ring = 1,
 };
 
 static const struct intel_device_info intel_sandybridge_d_info = {
-	.gen = 6,
+	.gen = 6, .num_pipes = 2,
 	.need_gfx_hws = 1, .has_hotplug = 1,
 	.has_bsd_ring = 1,
 	.has_blt_ring = 1,
@@ -239,7 +239,7 @@ static const struct intel_device_info intel_sandybridge_d_info = {
 };
 
 static const struct intel_device_info intel_sandybridge_m_info = {
-	.gen = 6, .is_mobile = 1,
+	.gen = 6, .is_mobile = 1, .num_pipes = 2,
 	.need_gfx_hws = 1, .has_hotplug = 1,
 	.has_fbc = 1,
 	.has_bsd_ring = 1,
@@ -249,7 +249,7 @@ static const struct intel_device_info intel_sandybridge_m_info = {
 };
 
 static const struct intel_device_info intel_ivybridge_d_info = {
-	.is_ivybridge = 1, .gen = 7,
+	.is_ivybridge = 1, .gen = 7, .num_pipes = 3,
 	.need_gfx_hws = 1, .has_hotplug = 1,
 	.has_bsd_ring = 1,
 	.has_blt_ring = 1,
@@ -258,7 +258,7 @@ static const struct intel_device_info intel_ivybridge_d_info = {
 };
 
 static const struct intel_device_info intel_ivybridge_m_info = {
-	.is_ivybridge = 1, .gen = 7, .is_mobile = 1,
+	.is_ivybridge = 1, .gen = 7, .is_mobile = 1, .num_pipes = 3,
 	.need_gfx_hws = 1, .has_hotplug = 1,
 	.has_fbc = 0,	/* FBC is not enabled on Ivybridge mobile yet */
 	.has_bsd_ring = 1,
@@ -268,7 +268,7 @@ static const struct intel_device_info intel_ivybridge_m_info = {
 };
 
 static const struct intel_device_info intel_valleyview_m_info = {
-	.gen = 7, .is_mobile = 1,
+	.gen = 7, .is_mobile = 1, .num_pipes = 2,
 	.need_gfx_hws = 1, .has_hotplug = 1,
 	.has_fbc = 0,
 	.has_bsd_ring = 1,
@@ -279,7 +279,7 @@ static const struct intel_device_info intel_valleyview_m_info = {
 };
 
 static const struct intel_device_info intel_valleyview_d_info = {
-	.gen = 7,
+	.gen = 7, .num_pipes = 2,
 	.need_gfx_hws = 1, .has_hotplug = 1,
 	.has_fbc = 0,
 	.has_bsd_ring = 1,
@@ -290,7 +290,7 @@ static const struct intel_device_info intel_valleyview_d_info = {
 };
 
 static const struct intel_device_info intel_haswell_d_info = {
-	.is_haswell = 1, .gen = 7,
+	.is_haswell = 1, .gen = 7, .num_pipes = 3,
 	.need_gfx_hws = 1, .has_hotplug = 1,
 	.has_bsd_ring = 1,
 	.has_blt_ring = 1,
@@ -299,7 +299,7 @@ static const struct intel_device_info intel_haswell_d_info = {
 };
 
 static const struct intel_device_info intel_haswell_m_info = {
-	.is_haswell = 1, .gen = 7, .is_mobile = 1,
+	.is_haswell = 1, .gen = 7, .is_mobile = 1, .num_pipes = 3,
 	.need_gfx_hws = 1, .has_hotplug = 1,
 	.has_bsd_ring = 1,
 	.has_blt_ring = 1,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ca6b215..587dca0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -93,7 +93,7 @@ enum port {
 	 I915_GEM_DOMAIN_INSTRUCTION | \
 	 I915_GEM_DOMAIN_VERTEX)
 
-#define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
+#define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)
 
 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
 	list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
@@ -341,6 +341,7 @@ struct drm_i915_gt_funcs {
 
 struct intel_device_info {
 	u32 display_mmio_offset;
+	u8 num_pipes:3;
 	u8 gen;
 	u8 is_mobile:1;
 	u8 is_i85x:1;
@@ -912,7 +913,6 @@ typedef struct drm_i915_private {
 	struct work_struct hotplug_work;
 	bool enable_hotplug_processing;
 
-	int num_pipe;
 	int num_pch_pll;
 
 	unsigned long cfb_size;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 2139714..b860f0b 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -254,10 +254,9 @@ static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
 			      struct timeval *vblank_time,
 			      unsigned flags)
 {
-	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_crtc *crtc;
 
-	if (pipe < 0 || pipe >= dev_priv->num_pipe) {
+	if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
 		DRM_ERROR("Invalid crtc %d\n", pipe);
 		return -EINVAL;
 	}
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 502cb28..23379e7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2335,10 +2335,10 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
 		return 0;
 	}
 
-	if(intel_crtc->plane > dev_priv->num_pipe) {
+	if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
 		DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
 				intel_crtc->plane,
-				dev_priv->num_pipe);
+				INTEL_INFO(dev)->num_pipes);
 		return -EINVAL;
 	}
 
@@ -5359,7 +5359,7 @@ static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
 		return false;
 	}
 
-	if (dev_priv->num_pipe == 2)
+	if (INTEL_INFO(dev)->num_pipes == 2)
 		return true;
 
 	switch (intel_crtc->pipe) {
@@ -8870,9 +8870,10 @@ void intel_modeset_init(struct drm_device *dev)
 	dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
 
 	DRM_DEBUG_KMS("%d display pipe%s available.\n",
-		      dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
+		      INTEL_INFO(dev)->num_pipes,
+		      INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
 
-	for (i = 0; i < dev_priv->num_pipe; i++) {
+	for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
 		intel_crtc_init(dev, i);
 		ret = intel_plane_init(dev, i);
 		if (ret)
@@ -8929,10 +8930,11 @@ static void intel_enable_pipe_a(struct drm_device *dev)
 static bool
 intel_check_plane_mapping(struct intel_crtc *crtc)
 {
-	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
+	struct drm_device *dev = crtc->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 reg, val;
 
-	if (dev_priv->num_pipe == 1)
+	if (INTEL_INFO(dev)->num_pipes == 1)
 		return true;
 
 	reg = DSPCNTR(!crtc->plane);
@@ -9366,10 +9368,9 @@ intel_display_print_error_state(struct seq_file *m,
 				struct drm_device *dev,
 				struct intel_display_error_state *error)
 {
-	drm_i915_private_t *dev_priv = dev->dev_private;
 	int i;
 
-	seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
+	seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
 	for_each_pipe(i) {
 		seq_printf(m, "Pipe [%d]:\n", i);
 		seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
diff --git a/drivers/gpu/drm/i915/intel_fb.c b/drivers/gpu/drm/i915/intel_fb.c
index 953ee73..dcdb1d3 100644
--- a/drivers/gpu/drm/i915/intel_fb.c
+++ b/drivers/gpu/drm/i915/intel_fb.c
@@ -240,7 +240,7 @@ int intel_fbdev_init(struct drm_device *dev)
 	ifbdev->helper.funcs = &intel_fb_helper_funcs;
 
 	ret = drm_fb_helper_init(dev, &ifbdev->helper,
-				 dev_priv->num_pipe,
+				 INTEL_INFO(dev)->num_pipes,
 				 INTELFB_CONN_LIMIT);
 	if (ret) {
 		kfree(ifbdev);
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index a3730e0..f1530f4 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -338,7 +338,7 @@ void intel_panel_enable_backlight(struct drm_device *dev,
 		if (tmp & BLM_PWM_ENABLE)
 			goto set_level;
 
-		if (dev_priv->num_pipe == 3)
+		if (INTEL_INFO(dev)->num_pipes == 3)
 			tmp &= ~BLM_PIPE_SELECT_IVB;
 		else
 			tmp &= ~BLM_PIPE_SELECT;
-- 
1.8.1.5

[PATCH 02/10] drm/i915: Support PCH no display

[Ben Widawsky]

GEN supports a fusing option which subtracts the PCH display (making the
CPU display also useless). In this configuration MMIO which gets decoded
to a certain range will hang the CPU.

For us, this is sort of the equivalent of having no pipes, and we can
easily modify some code to not do certain things with no pipes.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_dma.c      | 20 ++++++++++++++------
 drivers/gpu/drm/i915/intel_crt.c     |  3 +++
 drivers/gpu/drm/i915/intel_display.c | 10 ++++++++--
 drivers/gpu/drm/i915/intel_fb.c      |  3 +++
 drivers/gpu/drm/i915/intel_overlay.c |  3 +++
 5 files changed, 31 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index ebcfe2e..d925504 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1322,6 +1322,10 @@ static int i915_load_modeset_init(struct drm_device *dev)
 	/* Always safe in the mode setting case. */
 	/* FIXME: do pre/post-mode set stuff in core KMS code */
 	dev->vblank_disable_allowed = 1;
+	if (INTEL_INFO(dev)->num_pipes == 0) {
+		dev_priv->mm.suspended = 0;
+		return 0;
+	}
 
 	ret = intel_fbdev_init(dev);
 	if (ret)
@@ -1630,9 +1634,11 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 	mutex_init(&dev_priv->rps.hw_lock);
 	mutex_init(&dev_priv->modeset_restore_lock);
 
-	ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
-	if (ret)
-		goto out_gem_unload;
+	if (INTEL_INFO(dev)->num_pipes) {
+		ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
+		if (ret)
+			goto out_gem_unload;
+	}
 
 	/* Start out suspended */
 	dev_priv->mm.suspended = 1;
@@ -1647,9 +1653,11 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 
 	i915_setup_sysfs(dev);
 
-	/* Must be done after probing outputs */
-	intel_opregion_init(dev);
-	acpi_video_register();
+	if (INTEL_INFO(dev)->num_pipes) {
+		/* Must be done after probing outputs */
+		intel_opregion_init(dev);
+		acpi_video_register();
+	}
 
 	if (IS_GEN5(dev))
 		intel_gpu_ips_init(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index cfc9687..e794c6c 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -736,6 +736,9 @@ void intel_crt_init(struct drm_device *dev)
 	if (dmi_check_system(intel_no_crt))
 		return;
 
+	if (INTEL_INFO(dev)->num_pipes == 0)
+		return;
+
 	crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
 	if (!crt)
 		return;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 23379e7..d6dbffd 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7682,6 +7682,9 @@ intel_modeset_check_state(struct drm_device *dev)
 	struct intel_encoder *encoder;
 	struct intel_connector *connector;
 
+	if (INTEL_INFO(dev)->num_pipes == 0)
+		return;
+
 	list_for_each_entry(connector, &dev->mode_config.connector_list,
 			    base.head) {
 		/* This also checks the encoder/connector hw state with the
@@ -8326,7 +8329,9 @@ static void intel_setup_outputs(struct drm_device *dev)
 	if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
 		intel_crt_init(dev);
 
-	if (HAS_DDI(dev)) {
+	if (INTEL_INFO(dev)->num_pipes == 0) {
+		DRM_DEBUG_KMS("Skipping output detection\n");
+	} else if (HAS_DDI(dev)) {
 		int found;
 
 		/* Haswell uses DDI functions to detect digital outputs */
@@ -8443,7 +8448,8 @@ static void intel_setup_outputs(struct drm_device *dev)
 
 	intel_init_pch_refclk(dev);
 
-	drm_helper_move_panel_connectors_to_head(dev);
+	if (INTEL_INFO(dev)->num_pipes)
+		drm_helper_move_panel_connectors_to_head(dev);
 }
 
 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
diff --git a/drivers/gpu/drm/i915/intel_fb.c b/drivers/gpu/drm/i915/intel_fb.c
index dcdb1d3..5f825c2 100644
--- a/drivers/gpu/drm/i915/intel_fb.c
+++ b/drivers/gpu/drm/i915/intel_fb.c
@@ -295,6 +295,9 @@ void intel_fb_restore_mode(struct drm_device *dev)
 	struct drm_mode_config *config = &dev->mode_config;
 	struct drm_plane *plane;
 
+	if (!INTEL_INFO(dev)->num_pipes)
+		return;
+
 	drm_modeset_lock_all(dev);
 
 	ret = drm_fb_helper_restore_fbdev_mode(&dev_priv->fbdev->helper);
diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
index 67a2501..e7fbf2e 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -1323,6 +1323,9 @@ void intel_setup_overlay(struct drm_device *dev)
 	if (!HAS_OVERLAY(dev))
 		return;
 
+	if (INTEL_INFO(dev)->num_pipes == 0)
+		return;
+
 	overlay = kzalloc(sizeof(struct intel_overlay), GFP_KERNEL);
 	if (!overlay)
 		return;
-- 
1.8.1.5

[PATCH 03/10] drm/i915: PCH_NOP

[Ben Widawsky]

Given certain fusing options discussed in the previous patch, it's
possible to end up with platforms that normally have PCH but that PCH
doesn't actually exist. In many cases, this is easily remedied with
setting 0 pipes. This covers the other corners.

Requiring this is a symptom of improper code splitting (using
HAS_PCH_SPLIT instead of proper GEN checking, basically). I do not want
to fix this.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_drv.h      | 2 ++
 drivers/gpu/drm/i915/intel_display.c | 4 +++-
 drivers/gpu/drm/i915/intel_lvds.c    | 4 ++++
 3 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 587dca0..ceed199 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -461,6 +461,7 @@ enum intel_pch {
 	PCH_IBX,	/* Ibexpeak PCH */
 	PCH_CPT,	/* Cougarpoint PCH */
 	PCH_LPT,	/* Lynxpoint PCH */
+	PCH_NOP,
 };
 
 enum intel_sbi_destination {
@@ -1351,6 +1352,7 @@ struct drm_i915_file_private {
 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
+#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
 
 #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d6dbffd..1f0624e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5085,7 +5085,9 @@ static void lpt_init_pch_refclk(struct drm_device *dev)
  */
 void intel_init_pch_refclk(struct drm_device *dev)
 {
-	if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
+	if (HAS_PCH_NOP(dev))
+		return;
+	else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
 		ironlake_init_pch_refclk(dev);
 	else if (HAS_PCH_LPT(dev))
 		lpt_init_pch_refclk(dev);
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 6b24fc5..613ac43 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -1018,6 +1018,10 @@ static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)
 
 static bool intel_lvds_supported(struct drm_device *dev)
 {
+
+	if (HAS_PCH_NOP(dev))
+		return false;
+
 	/* With the introduction of the PCH we gained a dedicated
 	 * LVDS presence pin, use it. */
 	if (HAS_PCH_SPLIT(dev))
-- 
1.8.1.5

[PATCH 04/10] [v2] drm/i915: Don't touch South Display when PCH_NOP

[Ben Widawsky]

Interrupts, clock gating, and GMBUS are all within the, "this will hang
the CPU" range when we have PCH_NOP.

There is a bit of a hack in init clock gating. We want to do most of the
clock gating, but the part we skip will hang the system. It could
probably be abstracted a bit better, but I don't feel it's too
unsightly.

v2: Use inverse HAS_PCH_NOP check (Jani)

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_irq.c   | 20 ++++++++++++++------
 drivers/gpu/drm/i915/intel_bios.c |  3 +++
 drivers/gpu/drm/i915/intel_i2c.c  |  4 +++-
 drivers/gpu/drm/i915/intel_pm.c   |  3 ++-
 4 files changed, 22 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b860f0b..15b4668 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -738,14 +738,16 @@ static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
 			}
 		}
 
-		/* check event from PCH */
-		if (de_iir & DE_PCH_EVENT_IVB) {
-			u32 pch_iir = I915_READ(SDEIIR);
+		if (!HAS_PCH_NOP(dev)) {
+			/* check event from PCH */
+			if (de_iir & DE_PCH_EVENT_IVB) {
+				u32 pch_iir = I915_READ(SDEIIR);
 
-			cpt_irq_handler(dev, pch_iir);
+				cpt_irq_handler(dev, pch_iir);
 
-			/* clear PCH hotplug event before clear CPU irq */
-			I915_WRITE(SDEIIR, pch_iir);
+				/* clear PCH hotplug event before CPU irq */
+				I915_WRITE(SDEIIR, pch_iir);
+			}
 		}
 
 		I915_WRITE(DEIIR, de_iir);
@@ -1910,6 +1912,9 @@ static void ironlake_irq_preinstall(struct drm_device *dev)
 	I915_WRITE(GTIER, 0x0);
 	POSTING_READ(GTIER);
 
+	if (HAS_PCH_NOP(dev))
+		return;
+
 	/* south display irq */
 	I915_WRITE(SDEIMR, 0xffffffff);
 	I915_WRITE(SDEIER, 0x0);
@@ -1982,6 +1987,9 @@ static void ibx_irq_postinstall(struct drm_device *dev)
 		       SDE_GMBUS_CPT |
 		       SDE_AUX_MASK_CPT;
 
+	if (HAS_PCH_NOP(dev))
+		return;
+
 	I915_WRITE(SDEIIR, I915_READ(SDEIIR));
 	I915_WRITE(SDEIMR, ~mask);
 	I915_WRITE(SDEIER, mask);
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 55ffba1..194df27 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -692,6 +692,9 @@ intel_parse_bios(struct drm_device *dev)
 	struct bdb_header *bdb = NULL;
 	u8 __iomem *bios = NULL;
 
+	if (HAS_PCH_NOP(dev))
+		return -ENODEV;
+
 	init_vbt_defaults(dev_priv);
 
 	/* XXX Should this validation be moved to intel_opregion.c? */
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index acf8aec..fc19e49 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -513,7 +513,9 @@ int intel_setup_gmbus(struct drm_device *dev)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int ret, i;
 
-	if (HAS_PCH_SPLIT(dev))
+	if (HAS_PCH_NOP(dev))
+		return 0;
+	else if (HAS_PCH_SPLIT(dev))
 		dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA;
 	else if (IS_VALLEYVIEW(dev))
 		dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5479363..52203fd 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3874,7 +3874,8 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
 	snpcr |= GEN6_MBC_SNPCR_MED;
 	I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
 
-	cpt_init_clock_gating(dev);
+	if (HAS_PCH_NOP(dev))
+		cpt_init_clock_gating(dev);
 
 	gen6_check_mch_setup(dev);
 }
-- 
1.8.1.5

[PATCH 05/10] [v2] drm/i915: Don't initialize watermark stuff with PCH_NOP

[Ben Widawsky]

v2: Move check to the top (Chris)
Add BUG_ON for !ivybridge, since it's all we support for now (Ben)

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/intel_pm.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 52203fd..8e7908b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4153,7 +4153,12 @@ void intel_init_pm(struct drm_device *dev)
 		i915_ironlake_get_mem_freq(dev);
 
 	/* For FIFO watermark updates */
-	if (HAS_PCH_SPLIT(dev)) {
+	if (HAS_PCH_NOP(dev)) {
+		BUG_ON(!IS_IVYBRIDGE(dev));
+		dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
+		dev_priv->display.update_wm = NULL;
+		dev_priv->display.update_sprite_wm = NULL;
+	} else if (HAS_PCH_SPLIT(dev)) {
 		if (IS_GEN5(dev)) {
 			if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
 				dev_priv->display.update_wm = ironlake_update_wm;
@@ -4175,7 +4180,7 @@ void intel_init_pm(struct drm_device *dev)
 			dev_priv->display.init_clock_gating = gen6_init_clock_gating;
 		} else if (IS_IVYBRIDGE(dev)) {
 			/* FIXME: detect B0+ stepping and use auto training */
-			if (SNB_READ_WM0_LATENCY()) {
+			if (SNB_READ_WM0_LATENCY() && !HAS_PCH_NOP(dev)) {
 				dev_priv->display.update_wm = ivybridge_update_wm;
 				dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
 			} else {
-- 
1.8.1.5

[PATCH 06/10] drm/i915: PCH_NOP suspend/resume

[Ben Widawsky]

More registers we can't write.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_suspend.c | 57 ++++++++++++++++++++++++++-----------
 1 file changed, 41 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index c1e02b0..dd5766a 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -333,11 +333,19 @@ int i915_save_state(struct drm_device *dev)
 
 	mutex_lock(&dev->struct_mutex);
 
-	i915_save_display(dev);
+	if (!HAS_PCH_NOP(dev))
+		i915_save_display(dev);
 
 	if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
 		/* Interrupt state */
-		if (HAS_PCH_SPLIT(dev)) {
+		if (HAS_PCH_NOP(dev)) {
+			dev_priv->regfile.saveDEIER = I915_READ(DEIER);
+			dev_priv->regfile.saveDEIMR = I915_READ(DEIMR);
+			dev_priv->regfile.saveGTIER = I915_READ(GTIER);
+			dev_priv->regfile.saveGTIMR = I915_READ(GTIMR);
+			dev_priv->regfile.saveMCHBAR_RENDER_STANDBY =
+				I915_READ(RSTDBYCTL);
+		} else if (HAS_PCH_SPLIT(dev)) {
 			dev_priv->regfile.saveDEIER = I915_READ(DEIER);
 			dev_priv->regfile.saveDEIMR = I915_READ(DEIMR);
 			dev_priv->regfile.saveGTIER = I915_READ(GTIER);
@@ -361,13 +369,18 @@ int i915_save_state(struct drm_device *dev)
 	/* Memory Arbitration state */
 	dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
 
-	/* Scratch space */
-	for (i = 0; i < 16; i++) {
-		dev_priv->regfile.saveSWF0[i] = I915_READ(SWF00 + (i << 2));
-		dev_priv->regfile.saveSWF1[i] = I915_READ(SWF10 + (i << 2));
+	if (!HAS_PCH_NOP(dev)) {
+		/* Scratch space */
+		for (i = 0; i < 16; i++) {
+			dev_priv->regfile.saveSWF0[i] =
+				I915_READ(SWF00 + (i << 2));
+			dev_priv->regfile.saveSWF1[i] =
+				I915_READ(SWF10 + (i << 2));
+		}
+		for (i = 0; i < 3; i++)
+			dev_priv->regfile.saveSWF2[i] =
+				I915_READ(SWF30 + (i << 2));
 	}
-	for (i = 0; i < 3; i++)
-		dev_priv->regfile.saveSWF2[i] = I915_READ(SWF30 + (i << 2));
 
 	mutex_unlock(&dev->struct_mutex);
 
@@ -383,11 +396,17 @@ int i915_restore_state(struct drm_device *dev)
 
 	mutex_lock(&dev->struct_mutex);
 
-	i915_restore_display(dev);
+	if (!HAS_PCH_NOP(dev))
+		i915_restore_display(dev);
 
 	if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
 		/* Interrupt state */
-		if (HAS_PCH_SPLIT(dev)) {
+		if (HAS_PCH_NOP(dev)) {
+			I915_WRITE(DEIER, dev_priv->regfile.saveDEIER);
+			I915_WRITE(DEIMR, dev_priv->regfile.saveDEIMR);
+			I915_WRITE(GTIER, dev_priv->regfile.saveGTIER);
+			I915_WRITE(GTIMR, dev_priv->regfile.saveGTIMR);
+		} else if (HAS_PCH_SPLIT(dev)) {
 			I915_WRITE(DEIER, dev_priv->regfile.saveDEIER);
 			I915_WRITE(DEIMR, dev_priv->regfile.saveDEIMR);
 			I915_WRITE(GTIER, dev_priv->regfile.saveGTIER);
@@ -407,16 +426,22 @@ int i915_restore_state(struct drm_device *dev)
 	/* Memory arbitration state */
 	I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000);
 
-	for (i = 0; i < 16; i++) {
-		I915_WRITE(SWF00 + (i << 2), dev_priv->regfile.saveSWF0[i]);
-		I915_WRITE(SWF10 + (i << 2), dev_priv->regfile.saveSWF1[i]);
+	if (!HAS_PCH_NOP(dev)) {
+		for (i = 0; i < 16; i++) {
+			I915_WRITE(SWF00 + (i << 2),
+				   dev_priv->regfile.saveSWF0[i]);
+			I915_WRITE(SWF10 + (i << 2),
+				   dev_priv->regfile.saveSWF1[i]);
+		}
+		for (i = 0; i < 3; i++)
+			I915_WRITE(SWF30 + (i << 2),
+				   dev_priv->regfile.saveSWF2[i]);
 	}
-	for (i = 0; i < 3; i++)
-		I915_WRITE(SWF30 + (i << 2), dev_priv->regfile.saveSWF2[i]);
 
 	mutex_unlock(&dev->struct_mutex);
 
-	intel_i2c_reset(dev);
+	if (!HAS_PCH_NOP(dev))
+		intel_i2c_reset(dev);
 
 	return 0;
 }
-- 
1.8.1.5

[PATCH 07/10] drm/i915: Don't wait for PCH on reset

[Ben Widawsky]

BIOS should be setting this, but in case it doesn't...

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_gem.c | 3 +++
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 1417fc6..ee9c14c 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3986,6 +3986,9 @@ i915_gem_init_hw(struct drm_device *dev)
 	if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1))
 		I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);
 
+	if (HAS_PCH_NOP(dev))
+		I915_WRITE(GEN7_MSG_CTL, 0);
+
 	i915_gem_l3_remap(dev);
 
 	i915_gem_init_swizzling(dev);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4cf3ece..00b6a55 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3481,6 +3481,7 @@
 #define DISP_ARB_CTL	0x45000
 #define  DISP_TILE_SURFACE_SWIZZLING	(1<<13)
 #define  DISP_FBC_WM_DIS		(1<<15)
+#define GEN7_MSG_CTL	0x45010
 
 /* GEN7 chicken */
 #define GEN7_COMMON_SLICE_CHICKEN1		0x7010
-- 
1.8.1.5

[PATCH 08/10] drm/i915: Set PCH_NOP

[Ben Widawsky]

Set up PCH_NOP when we match a certain platform.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_drv.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 8ff83e9..a63abd7 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -398,11 +398,22 @@ static const struct pci_device_id pciidlist[] = {		/* aka */
 MODULE_DEVICE_TABLE(pci, pciidlist);
 #endif
 
+static bool intel_pch_displayless(struct drm_device *dev)
+{
+	return false;
+}
+
 void intel_detect_pch(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct pci_dev *pch;
 
+	if (intel_pch_displayless(dev)) {
+		dev_priv->pch_type = PCH_NOP;
+		dev_priv->num_pch_pll = 0;
+		return;
+	}
+
 	/*
 	 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 	 * make graphics device passthrough work easy for VMM, that only
-- 
1.8.1.5

[PATCH 09/10] [v2] drm/i915: Introduce GEN7_FEATURES for device info

[Ben Widawsky]

Recommended by Chris.

v2: Make it GEN7_FEATURES, and use it for vlv and hsw also (Ben)

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_drv.c | 60 ++++++++++++++++-------------------------
 1 file changed, 23 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index a63abd7..a67e8c7 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -248,63 +248,49 @@ static const struct intel_device_info intel_sandybridge_m_info = {
 	.has_force_wake = 1,
 };
 
+#define GEN7_FEATURES  \
+	.gen = 7, .num_pipes = 3, \
+	.need_gfx_hws = 1, .has_hotplug = 1, \
+	.has_bsd_ring = 1, \
+	.has_blt_ring = 1, \
+	.has_llc = 1, \
+	.has_force_wake = 1
+
 static const struct intel_device_info intel_ivybridge_d_info = {
-	.is_ivybridge = 1, .gen = 7, .num_pipes = 3,
-	.need_gfx_hws = 1, .has_hotplug = 1,
-	.has_bsd_ring = 1,
-	.has_blt_ring = 1,
-	.has_llc = 1,
-	.has_force_wake = 1,
+	GEN7_FEATURES,
+	.is_ivybridge = 1,
 };
 
 static const struct intel_device_info intel_ivybridge_m_info = {
-	.is_ivybridge = 1, .gen = 7, .is_mobile = 1, .num_pipes = 3,
-	.need_gfx_hws = 1, .has_hotplug = 1,
-	.has_fbc = 0,	/* FBC is not enabled on Ivybridge mobile yet */
-	.has_bsd_ring = 1,
-	.has_blt_ring = 1,
-	.has_llc = 1,
-	.has_force_wake = 1,
+	GEN7_FEATURES,
+	.is_ivybridge = 1,
+	.is_mobile = 1,
 };
 
 static const struct intel_device_info intel_valleyview_m_info = {
-	.gen = 7, .is_mobile = 1, .num_pipes = 2,
-	.need_gfx_hws = 1, .has_hotplug = 1,
-	.has_fbc = 0,
-	.has_bsd_ring = 1,
-	.has_blt_ring = 1,
+	GEN7_FEATURES,
+	.is_mobile = 1,
+	.num_pipes = 2,
 	.is_valleyview = 1,
 	.display_mmio_offset = VLV_DISPLAY_BASE,
-	.has_force_wake = 1,
 };
 
 static const struct intel_device_info intel_valleyview_d_info = {
-	.gen = 7, .num_pipes = 2,
-	.need_gfx_hws = 1, .has_hotplug = 1,
-	.has_fbc = 0,
-	.has_bsd_ring = 1,
-	.has_blt_ring = 1,
+	GEN7_FEATURES,
+	.num_pipes = 2,
 	.is_valleyview = 1,
 	.display_mmio_offset = VLV_DISPLAY_BASE,
-	.has_force_wake = 1,
 };
 
 static const struct intel_device_info intel_haswell_d_info = {
-	.is_haswell = 1, .gen = 7, .num_pipes = 3,
-	.need_gfx_hws = 1, .has_hotplug = 1,
-	.has_bsd_ring = 1,
-	.has_blt_ring = 1,
-	.has_llc = 1,
-	.has_force_wake = 1,
+	GEN7_FEATURES,
+	.is_haswell = 1,
 };
 
 static const struct intel_device_info intel_haswell_m_info = {
-	.is_haswell = 1, .gen = 7, .is_mobile = 1, .num_pipes = 3,
-	.need_gfx_hws = 1, .has_hotplug = 1,
-	.has_bsd_ring = 1,
-	.has_blt_ring = 1,
-	.has_llc = 1,
-	.has_force_wake = 1,
+	GEN7_FEATURES,
+	.is_haswell = 1,
+	.is_mobile = 1,
 };
 
 static const struct pci_device_id pciidlist[] = {		/* aka */
-- 
1.8.1.5

[PATCH 10/10] [v2] drm/i915: Add a pipeless ivybridge configuration

[Ben Widawsky]

FIXME: This is based on some HW being used for a demo. We should
probably wait until we have confirmation on the IDs before upstreaming
this patch.

v2: Use GEN7_FEATURES (Chris)

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_drv.c | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index a67e8c7..bd8dfa6 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -135,6 +135,16 @@ extern int intel_agp_enabled;
 	.subdevice = PCI_ANY_ID,		\
 	.driver_data = (unsigned long) info }
 
+#define INTEL_QUANTA_VGA_DEVICE(info) {		\
+	.class = PCI_BASE_CLASS_DISPLAY << 16,	\
+	.class_mask = 0xff0000,			\
+	.vendor = 0x8086,			\
+	.device = 0x16a,			\
+	.subvendor = 0x152d,			\
+	.subdevice = 0x8990,			\
+	.driver_data = (unsigned long) info }
+
+
 static const struct intel_device_info intel_i830_info = {
 	.gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 	.has_overlay = 1, .overlay_needs_physical = 1,
@@ -267,6 +277,12 @@ static const struct intel_device_info intel_ivybridge_m_info = {
 	.is_mobile = 1,
 };
 
+static const struct intel_device_info intel_ivybridge_q_info = {
+	GEN7_FEATURES,
+	.is_ivybridge = 1,
+	.num_pipes = 0, /* legal, last one wins */
+};
+
 static const struct intel_device_info intel_valleyview_m_info = {
 	GEN7_FEATURES,
 	.is_mobile = 1,
@@ -337,6 +353,7 @@ static const struct pci_device_id pciidlist[] = {		/* aka */
 	INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
 	INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
 	INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
+	INTEL_QUANTA_VGA_DEVICE(&intel_ivybridge_q_info), /* Quanta transcode */
 	INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
 	INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
 	INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
@@ -386,7 +403,7 @@ MODULE_DEVICE_TABLE(pci, pciidlist);
 
 static bool intel_pch_displayless(struct drm_device *dev)
 {
-	return false;
+	return INTEL_INFO(dev) == &intel_ivybridge_q_info;
 }
 
 void intel_detect_pch(struct drm_device *dev)
-- 
1.8.1.5

Re: [PATCH 10/10] [v2] drm/i915: Add a pipeless ivybridge configuration

[Daniel Vetter]

On Fri, Mar 15, 2013 at 11:17:55AM -0700, Ben Widawsky wrote:
> FIXME: This is based on some HW being used for a demo. We should
> probably wait until we have confirmation on the IDs before upstreaming
> this patch.

I don't mind too much if we need to fixup the device after the fact, but
checking whether this is the shipping configuration shouldn't hurt.

More important is probably whether there's any quanta platform with the
same sdev/svendor ids without a fused pch. In that case I guess we need to
check for something else (maybe some fuse flags in the pch?).

Anyway, I've done a pretty careful review of everything, mostly looking to
reduce the impact of this feature on our code. So if you respin and
quickly test this on an real ivb (just for paranoia) and the special box
I'll merge it right away. Imo the maintenance burned is really small, so
I'm not against merging this in the demo stage.

Cheers, Daniel
> 
> v2: Use GEN7_FEATURES (Chris)
> 
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> ---
>  drivers/gpu/drm/i915/i915_drv.c | 19 ++++++++++++++++++-
>  1 file changed, 18 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index a67e8c7..bd8dfa6 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -135,6 +135,16 @@ extern int intel_agp_enabled;
>  	.subdevice = PCI_ANY_ID,		\
>  	.driver_data = (unsigned long) info }
>  
> +#define INTEL_QUANTA_VGA_DEVICE(info) {		\
> +	.class = PCI_BASE_CLASS_DISPLAY << 16,	\
> +	.class_mask = 0xff0000,			\
> +	.vendor = 0x8086,			\
> +	.device = 0x16a,			\
> +	.subvendor = 0x152d,			\
> +	.subdevice = 0x8990,			\
> +	.driver_data = (unsigned long) info }
> +
> +
>  static const struct intel_device_info intel_i830_info = {
>  	.gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
>  	.has_overlay = 1, .overlay_needs_physical = 1,
> @@ -267,6 +277,12 @@ static const struct intel_device_info intel_ivybridge_m_info = {
>  	.is_mobile = 1,
>  };
>  
> +static const struct intel_device_info intel_ivybridge_q_info = {
> +	GEN7_FEATURES,
> +	.is_ivybridge = 1,
> +	.num_pipes = 0, /* legal, last one wins */
> +};
> +
>  static const struct intel_device_info intel_valleyview_m_info = {
>  	GEN7_FEATURES,
>  	.is_mobile = 1,
> @@ -337,6 +353,7 @@ static const struct pci_device_id pciidlist[] = {		/* aka */
>  	INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
>  	INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
>  	INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
> +	INTEL_QUANTA_VGA_DEVICE(&intel_ivybridge_q_info), /* Quanta transcode */
>  	INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
>  	INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
>  	INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
> @@ -386,7 +403,7 @@ MODULE_DEVICE_TABLE(pci, pciidlist);
>  
>  static bool intel_pch_displayless(struct drm_device *dev)
>  {
> -	return false;
> +	return INTEL_INFO(dev) == &intel_ivybridge_q_info;
>  }
>  
>  void intel_detect_pch(struct drm_device *dev)
> -- 
> 1.8.1.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 10/10] [v2] drm/i915: Add a pipeless ivybridge configuration

[Ben Widawsky]

On Sun, Mar 17, 2013 at 10:42:33PM +0100, Daniel Vetter wrote:
> On Fri, Mar 15, 2013 at 11:17:55AM -0700, Ben Widawsky wrote:
> > FIXME: This is based on some HW being used for a demo. We should
> > probably wait until we have confirmation on the IDs before upstreaming
> > this patch.
> 
> I don't mind too much if we need to fixup the device after the fact, but
> checking whether this is the shipping configuration shouldn't hurt.
> 
> More important is probably whether there's any quanta platform with the
> same sdev/svendor ids without a fused pch. In that case I guess we need to
> check for something else (maybe some fuse flags in the pch?).

I highly doubt it, but I don't know how to prove it. From what I gather
on the internet and parsing through the limited uses in the kernel
today, the subvendor/subdevice is unique.

> 
> Anyway, I've done a pretty careful review of everything, mostly looking to
> reduce the impact of this feature on our code. So if you respin and
> quickly test this on an real ivb (just for paranoia) and the special box
> I'll merge it right away. Imo the maintenance burned is really small, so
> I'm not against merging this in the demo stage.

I've rebased on nightly and tried to apply all the requests (assuming I
didn't miss any). Because I am at home today, and testing displayless at
home is sort of a pain, this is untested on both regular IVB (the rebase
did have a conflict), and the Quanta server.

I can test it on regular IVB tomorrow, and I'll begin trying to get it
tested on the Quanta thing ASAP, but it could be a few days. Meanwhile,
I've pushed the respun patches here:
http://cgit.freedesktop.org/~bwidawsk/drm-intel/log/?h=pch_displayless

> 
> Cheers, Daniel

Thanks for the review.
[snip]

> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch

-- 
Ben Widawsky, Intel Open Source Technology Center

Re: [PATCH 10/10] [v2] drm/i915: Add a pipeless ivybridge configuration

[Jesse Barnes]

On Tue, 19 Mar 2013 11:49:49 -0700
Ben Widawsky <ben@bwidawsk.net> wrote:

> On Sun, Mar 17, 2013 at 10:42:33PM +0100, Daniel Vetter wrote:
> > On Fri, Mar 15, 2013 at 11:17:55AM -0700, Ben Widawsky wrote:
> > > FIXME: This is based on some HW being used for a demo. We should
> > > probably wait until we have confirmation on the IDs before upstreaming
> > > this patch.
> > 
> > I don't mind too much if we need to fixup the device after the fact, but
> > checking whether this is the shipping configuration shouldn't hurt.
> > 
> > More important is probably whether there's any quanta platform with the
> > same sdev/svendor ids without a fused pch. In that case I guess we need to
> > check for something else (maybe some fuse flags in the pch?).
> 
> I highly doubt it, but I don't know how to prove it. From what I gather
> on the internet and parsing through the limited uses in the kernel
> today, the subvendor/subdevice is unique.

I believe this is just an early board; for production I've requested a
unique PCI ID.  We'll see what happens...  If nothing else, the
existing subvendor/subdev is good for testing the new code.  We can
drop it if/when we get a better check.

-- 
Jesse Barnes, Intel Open Source Technology Center

Re: [PATCH 09/10] [v2] drm/i915: Introduce GEN7_FEATURES for device info

[Daniel Vetter]

On Fri, Mar 15, 2013 at 11:17:54AM -0700, Ben Widawsky wrote:
> Recommended by Chris.
> 
> v2: Make it GEN7_FEATURES, and use it for vlv and hsw also (Ben)
> 
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Queued for -next, thanks for the patch.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 02/10] drm/i915: Support PCH no display

[Ville Syrjälä]

On Fri, Mar 15, 2013 at 11:17:47AM -0700, Ben Widawsky wrote:
> GEN supports a fusing option which subtracts the PCH display (making the
> CPU display also useless). In this configuration MMIO which gets decoded
> to a certain range will hang the CPU.
> 
> For us, this is sort of the equivalent of having no pipes, and we can
> easily modify some code to not do certain things with no pipes.
> 
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> ---
>  drivers/gpu/drm/i915/i915_dma.c      | 20 ++++++++++++++------
>  drivers/gpu/drm/i915/intel_crt.c     |  3 +++
>  drivers/gpu/drm/i915/intel_display.c | 10 ++++++++--
>  drivers/gpu/drm/i915/intel_fb.c      |  3 +++
>  drivers/gpu/drm/i915/intel_overlay.c |  3 +++
>  5 files changed, 31 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index ebcfe2e..d925504 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -1322,6 +1322,10 @@ static int i915_load_modeset_init(struct drm_device *dev)
>  	/* Always safe in the mode setting case. */
>  	/* FIXME: do pre/post-mode set stuff in core KMS code */
>  	dev->vblank_disable_allowed = 1;
> +	if (INTEL_INFO(dev)->num_pipes == 0) {
> +		dev_priv->mm.suspended = 0;
> +		return 0;
> +	}
>  
>  	ret = intel_fbdev_init(dev);
>  	if (ret)
> @@ -1630,9 +1634,11 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
>  	mutex_init(&dev_priv->rps.hw_lock);
>  	mutex_init(&dev_priv->modeset_restore_lock);
>  
> -	ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
> -	if (ret)
> -		goto out_gem_unload;
> +	if (INTEL_INFO(dev)->num_pipes) {
> +		ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
> +		if (ret)
> +			goto out_gem_unload;
> +	}
>  
>  	/* Start out suspended */
>  	dev_priv->mm.suspended = 1;
> @@ -1647,9 +1653,11 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
>  
>  	i915_setup_sysfs(dev);
>  
> -	/* Must be done after probing outputs */
> -	intel_opregion_init(dev);
> -	acpi_video_register();
> +	if (INTEL_INFO(dev)->num_pipes) {
> +		/* Must be done after probing outputs */
> +		intel_opregion_init(dev);
> +		acpi_video_register();
> +	}
>  
>  	if (IS_GEN5(dev))
>  		intel_gpu_ips_init(dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
> index cfc9687..e794c6c 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -736,6 +736,9 @@ void intel_crt_init(struct drm_device *dev)
>  	if (dmi_check_system(intel_no_crt))
>  		return;
>  
> +	if (INTEL_INFO(dev)->num_pipes == 0)
> +		return;
> +
>  	crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
>  	if (!crt)
>  		return;
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 23379e7..d6dbffd 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -7682,6 +7682,9 @@ intel_modeset_check_state(struct drm_device *dev)
>  	struct intel_encoder *encoder;
>  	struct intel_connector *connector;
>  
> +	if (INTEL_INFO(dev)->num_pipes == 0)
> +		return;
> +
>  	list_for_each_entry(connector, &dev->mode_config.connector_list,
>  			    base.head) {
>  		/* This also checks the encoder/connector hw state with the
> @@ -8326,7 +8329,9 @@ static void intel_setup_outputs(struct drm_device *dev)
>  	if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
>  		intel_crt_init(dev);
>  
> -	if (HAS_DDI(dev)) {
> +	if (INTEL_INFO(dev)->num_pipes == 0) {
> +		DRM_DEBUG_KMS("Skipping output detection\n");

Wouldn't it be better to skip intel_setup_outputs() entirely? You could
then drop the intel_crt_init() hunk too.

> +	} else if (HAS_DDI(dev)) {
>  		int found;
>  
>  		/* Haswell uses DDI functions to detect digital outputs */
> @@ -8443,7 +8448,8 @@ static void intel_setup_outputs(struct drm_device *dev)
>  
>  	intel_init_pch_refclk(dev);
>  
> -	drm_helper_move_panel_connectors_to_head(dev);
> +	if (INTEL_INFO(dev)->num_pipes)
> +		drm_helper_move_panel_connectors_to_head(dev);
>  }
>  
>  static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
> diff --git a/drivers/gpu/drm/i915/intel_fb.c b/drivers/gpu/drm/i915/intel_fb.c
> index dcdb1d3..5f825c2 100644
> --- a/drivers/gpu/drm/i915/intel_fb.c
> +++ b/drivers/gpu/drm/i915/intel_fb.c
> @@ -295,6 +295,9 @@ void intel_fb_restore_mode(struct drm_device *dev)
>  	struct drm_mode_config *config = &dev->mode_config;
>  	struct drm_plane *plane;
>  
> +	if (!INTEL_INFO(dev)->num_pipes)
> +		return;
> +
>  	drm_modeset_lock_all(dev);
>  
>  	ret = drm_fb_helper_restore_fbdev_mode(&dev_priv->fbdev->helper);
> diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
> index 67a2501..e7fbf2e 100644
> --- a/drivers/gpu/drm/i915/intel_overlay.c
> +++ b/drivers/gpu/drm/i915/intel_overlay.c
> @@ -1323,6 +1323,9 @@ void intel_setup_overlay(struct drm_device *dev)
>  	if (!HAS_OVERLAY(dev))
>  		return;
>  
> +	if (INTEL_INFO(dev)->num_pipes == 0)
> +		return;
> +
>  	overlay = kzalloc(sizeof(struct intel_overlay), GFP_KERNEL);
>  	if (!overlay)
>  		return;
> -- 
> 1.8.1.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC