From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:43198) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UMg6t-0001fx-39 for qemu-devel@nongnu.org; Mon, 01 Apr 2013 10:53:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UMg6m-0006JU-0L for qemu-devel@nongnu.org; Mon, 01 Apr 2013 10:53:23 -0400 Received: from hall.aurel32.net ([2001:470:1f15:c4f::1]:52508) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UMg6l-0006JN-QW for qemu-devel@nongnu.org; Mon, 01 Apr 2013 10:53:15 -0400 Date: Mon, 1 Apr 2013 16:53:04 +0200 From: Aurelien Jarno Message-ID: <20130401145304.GI17634@hall.aurel32.net> References: <1362443590-28191-1-git-send-email-rth@twiddle.net> <1362443590-28191-10-git-send-email-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline In-Reply-To: <1362443590-28191-10-git-send-email-rth@twiddle.net> Sender: Aurelien Jarno Subject: Re: [Qemu-devel] [PATCH v2 09/27] tcg-ppc64: Rearrange integer constant constraints List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson Cc: av1474@comtv.ru, qemu-devel@nongnu.org On Mon, Mar 04, 2013 at 04:32:52PM -0800, Richard Henderson wrote: > We'll need a zero, and Z makes more sense for that. Make sure we > have a full compliment of signed and unsigned 16 and 32-bit tests. > > Signed-off-by: Richard Henderson > --- > tcg/ppc64/tcg-target.c | 43 +++++++++++++++++++++++++++++++++---------- > 1 file changed, 33 insertions(+), 10 deletions(-) > > diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c > index 31b0cb7..0e4826d 100644 > --- a/tcg/ppc64/tcg-target.c > +++ b/tcg/ppc64/tcg-target.c > @@ -22,7 +22,11 @@ > * THE SOFTWARE. > */ > > -#define TCG_CT_CONST_U32 0x100 > +#define TCG_CT_CONST_S16 0x100 > +#define TCG_CT_CONST_U16 0x200 > +#define TCG_CT_CONST_S32 0x400 > +#define TCG_CT_CONST_U32 0x800 > +#define TCG_CT_CONST_ZERO 0x1000 > > static uint8_t *tb_ret_addr; > > @@ -242,9 +246,21 @@ static int target_parse_constraint (TCGArgConstraint *ct, const char **pct_str) > tcg_regset_reset_reg (ct->u.regs, TCG_REG_R6); > #endif > break; > - case 'Z': > + case 'I': > + ct->ct |= TCG_CT_CONST_S16; > + break; > + case 'J': > + ct->ct |= TCG_CT_CONST_U16; > + break; > + case 'T': > + ct->ct |= TCG_CT_CONST_S32; > + break; > + case 'U': > ct->ct |= TCG_CT_CONST_U32; > break; > + case 'Z': > + ct->ct |= TCG_CT_CONST_ZERO; > + break; > default: > return -1; > } > @@ -257,13 +273,20 @@ static int target_parse_constraint (TCGArgConstraint *ct, const char **pct_str) > static int tcg_target_const_match (tcg_target_long val, > const TCGArgConstraint *arg_ct) > { > - int ct; > - > - ct = arg_ct->ct; > - if (ct & TCG_CT_CONST) > + int ct = arg_ct->ct; > + if (ct & TCG_CT_CONST) { > + return 1; > + } else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) { > + return 1; > + } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) { > return 1; > - else if ((ct & TCG_CT_CONST_U32) && (val == (uint32_t) val)) > + } else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) { > return 1; > + } else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) { > + return 1; > + } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) { > + return 1; > + } > return 0; > } > > @@ -1607,9 +1630,9 @@ static const TCGTargetOpDef ppc_op_defs[] = { > > { INDEX_op_add_i64, { "r", "r", "ri" } }, > { INDEX_op_sub_i64, { "r", "r", "ri" } }, > - { INDEX_op_and_i64, { "r", "r", "rZ" } }, > - { INDEX_op_or_i64, { "r", "r", "rZ" } }, > - { INDEX_op_xor_i64, { "r", "r", "rZ" } }, > + { INDEX_op_and_i64, { "r", "r", "rU" } }, > + { INDEX_op_or_i64, { "r", "r", "rU" } }, > + { INDEX_op_xor_i64, { "r", "r", "rU" } }, > > { INDEX_op_shl_i64, { "r", "r", "ri" } }, > { INDEX_op_shr_i64, { "r", "r", "ri" } }, Reviewed-by: Aurelien Jarno -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurelien@aurel32.net http://www.aurel32.net