From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:44140) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UMgC0-0002Sb-DZ for qemu-devel@nongnu.org; Mon, 01 Apr 2013 10:58:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UMgBw-00083g-IL for qemu-devel@nongnu.org; Mon, 01 Apr 2013 10:58:40 -0400 Received: from hall.aurel32.net ([2001:470:1f15:c4f::1]:52558) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UMgBw-00083W-7d for qemu-devel@nongnu.org; Mon, 01 Apr 2013 10:58:36 -0400 Date: Mon, 1 Apr 2013 16:58:33 +0200 From: Aurelien Jarno Message-ID: <20130401145833.GD19864@ohm.aurel32.net> References: <1362443590-28191-1-git-send-email-rth@twiddle.net> <1362443590-28191-19-git-send-email-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline In-Reply-To: <1362443590-28191-19-git-send-email-rth@twiddle.net> Subject: Re: [Qemu-devel] [PATCH v2 18/27] tcg-ppc64: Implement compound logicals List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson Cc: av1474@comtv.ru, qemu-devel@nongnu.org On Mon, Mar 04, 2013 at 04:33:01PM -0800, Richard Henderson wrote: > Mostly copied from the ppc32 port. > > Signed-off-by: Richard Henderson > --- > tcg/ppc64/tcg-target.c | 34 ++++++++++++++++++++++++++++++++++ > tcg/ppc64/tcg-target.h | 20 ++++++++++---------- > 2 files changed, 44 insertions(+), 10 deletions(-) > > diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c > index 576effc..a1be15a 100644 > --- a/tcg/ppc64/tcg-target.c > +++ b/tcg/ppc64/tcg-target.c > @@ -385,6 +385,10 @@ static int tcg_target_const_match (tcg_target_long val, > #define NOR XO31(124) > #define CNTLZW XO31( 26) > #define CNTLZD XO31( 58) > +#define ANDC XO31( 60) > +#define ORC XO31(412) > +#define EQV XO31(284) > +#define NAND XO31(476) > > #define MULLD XO31(233) > #define MULHD XO31( 73) > @@ -1415,6 +1419,26 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args, > tcg_out32(s, XOR | SAB(a1, a0, a2)); > } > break; > + case INDEX_op_andc_i32: > + case INDEX_op_andc_i64: > + tcg_out32(s, ANDC | SAB(args[1], args[0], args[2])); > + break; > + case INDEX_op_orc_i32: > + case INDEX_op_orc_i64: > + tcg_out32(s, ORC | SAB(args[1], args[0], args[2])); > + break; > + case INDEX_op_eqv_i32: > + case INDEX_op_eqv_i64: > + tcg_out32(s, EQV | SAB(args[1], args[0], args[2])); > + break; > + case INDEX_op_nand_i32: > + case INDEX_op_nand_i64: > + tcg_out32(s, NAND | SAB(args[1], args[0], args[2])); > + break; > + case INDEX_op_nor_i32: > + case INDEX_op_nor_i64: > + tcg_out32(s, NOR | SAB(args[1], args[0], args[2])); > + break; > > case INDEX_op_mul_i32: > if (const_args[2]) { > @@ -1788,6 +1812,11 @@ static const TCGTargetOpDef ppc_op_defs[] = { > { INDEX_op_and_i32, { "r", "r", "ri" } }, > { INDEX_op_or_i32, { "r", "r", "ri" } }, > { INDEX_op_xor_i32, { "r", "r", "ri" } }, > + { INDEX_op_andc_i32, { "r", "r", "r" } }, > + { INDEX_op_orc_i32, { "r", "r", "r" } }, > + { INDEX_op_eqv_i32, { "r", "r", "r" } }, > + { INDEX_op_nand_i32, { "r", "r", "r" } }, > + { INDEX_op_nor_i32, { "r", "r", "r" } }, > > { INDEX_op_shl_i32, { "r", "r", "ri" } }, > { INDEX_op_shr_i32, { "r", "r", "ri" } }, > @@ -1806,6 +1835,11 @@ static const TCGTargetOpDef ppc_op_defs[] = { > { INDEX_op_and_i64, { "r", "r", "rU" } }, > { INDEX_op_or_i64, { "r", "r", "rU" } }, > { INDEX_op_xor_i64, { "r", "r", "rU" } }, > + { INDEX_op_andc_i64, { "r", "r", "r" } }, > + { INDEX_op_orc_i64, { "r", "r", "r" } }, > + { INDEX_op_eqv_i64, { "r", "r", "r" } }, > + { INDEX_op_nand_i64, { "r", "r", "r" } }, > + { INDEX_op_nor_i64, { "r", "r", "r" } }, > > { INDEX_op_shl_i64, { "r", "r", "ri" } }, > { INDEX_op_shr_i64, { "r", "r", "ri" } }, > diff --git a/tcg/ppc64/tcg-target.h b/tcg/ppc64/tcg-target.h > index d8e1820..35414cf 100644 > --- a/tcg/ppc64/tcg-target.h > +++ b/tcg/ppc64/tcg-target.h > @@ -82,11 +82,11 @@ typedef enum { > #define TCG_TARGET_HAS_bswap32_i32 1 > #define TCG_TARGET_HAS_not_i32 1 > #define TCG_TARGET_HAS_neg_i32 1 > -#define TCG_TARGET_HAS_andc_i32 0 > -#define TCG_TARGET_HAS_orc_i32 0 > -#define TCG_TARGET_HAS_eqv_i32 0 > -#define TCG_TARGET_HAS_nand_i32 0 > -#define TCG_TARGET_HAS_nor_i32 0 > +#define TCG_TARGET_HAS_andc_i32 1 > +#define TCG_TARGET_HAS_orc_i32 1 > +#define TCG_TARGET_HAS_eqv_i32 1 > +#define TCG_TARGET_HAS_nand_i32 1 > +#define TCG_TARGET_HAS_nor_i32 1 > #define TCG_TARGET_HAS_deposit_i32 0 > #define TCG_TARGET_HAS_movcond_i32 0 > #define TCG_TARGET_HAS_add2_i32 0 > @@ -105,11 +105,11 @@ typedef enum { > #define TCG_TARGET_HAS_bswap64_i64 1 > #define TCG_TARGET_HAS_not_i64 1 > #define TCG_TARGET_HAS_neg_i64 1 > -#define TCG_TARGET_HAS_andc_i64 0 > -#define TCG_TARGET_HAS_orc_i64 0 > -#define TCG_TARGET_HAS_eqv_i64 0 > -#define TCG_TARGET_HAS_nand_i64 0 > -#define TCG_TARGET_HAS_nor_i64 0 > +#define TCG_TARGET_HAS_andc_i64 1 > +#define TCG_TARGET_HAS_orc_i64 1 > +#define TCG_TARGET_HAS_eqv_i64 1 > +#define TCG_TARGET_HAS_nand_i64 1 > +#define TCG_TARGET_HAS_nor_i64 1 > #define TCG_TARGET_HAS_deposit_i64 0 > #define TCG_TARGET_HAS_movcond_i64 0 > #define TCG_TARGET_HAS_add2_i64 0 Reviewed-by: Aurelien Jarno -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurelien@aurel32.net http://www.aurel32.net