From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH] drm/i915: Don't override PPGTT cacheability on HSW Date: Thu, 4 Apr 2013 14:31:09 +0300 Message-ID: <20130404113109.GZ4469@intel.com> References: <1365012390-6465-1-git-send-email-ben@bwidawsk.net> <515C8048.1080503@whitecape.org> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga14.intel.com (mga14.intel.com [143.182.124.37]) by gabe.freedesktop.org (Postfix) with ESMTP id 83ABBE5C31 for ; Thu, 4 Apr 2013 04:31:24 -0700 (PDT) Content-Disposition: inline In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Daniel Vetter Cc: intel-gfx , Ben Widawsky List-Id: intel-gfx@lists.freedesktop.org On Wed, Apr 03, 2013 at 10:08:26PM +0200, Daniel Vetter wrote: > On Wed, Apr 3, 2013 at 9:33 PM, Daniel Vetter wrote: > > So I've checked hsw bspec and the problem is that hw guys again > > changed the bits around a bit, and I think on HSW we actually want > > (0x8 << 3) instead of what's currently there. > = > Meh, I've screwed up reading the tables, 0x3 << 3 is what we imo want, > so nothing needs to be changed. Sorry for the confusion. Shouldn't it be (1<<3) on IVB (for just LLC w/o GFDT), and (3<<3) on the rest? Also what about the GAC_ECO_BITS register? BSpec tells me it exists on IVB and HSW as well. It also seems to have a bit very similar to ECOCHK_SNB_BIT but we don't actually set it on SNB. -- = Ville Syrj=E4l=E4 Intel OTC