From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 1/3] drm/i915: Enable FBC at Haswell. Date: Tue, 9 Apr 2013 11:35:34 +0300 Message-ID: <20130409083534.GJ4469@intel.com> References: <1365457784-3412-1-git-send-email-rodrigo.vivi@gmail.com> <1365457784-3412-2-git-send-email-rodrigo.vivi@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id B9B5EE6002 for ; Tue, 9 Apr 2013 01:35:38 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1365457784-3412-2-git-send-email-rodrigo.vivi@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Rodrigo Vivi Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Mon, Apr 08, 2013 at 06:49:42PM -0300, Rodrigo Vivi wrote: > This patch introduce Frame Buffer Compression (FBC) support for HSW. > It adds a new function haswell_enable_fbc to avoid getting > ironlake_enable_fbc messed with many IS_HASWELL checks. > = > Signed-off-by: Rodrigo Vivi > --- > drivers/gpu/drm/i915/i915_drv.c | 1 + > drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ > drivers/gpu/drm/i915/intel_pm.c | 44 +++++++++++++++++++++++++++++++++++= +++++- > 3 files changed, 50 insertions(+), 1 deletion(-) > = > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_= drv.c > index 0cfc778..88fd6fb 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -291,6 +291,7 @@ static const struct intel_device_info intel_haswell_m= _info =3D { > GEN7_FEATURES, > .is_haswell =3D 1, > .is_mobile =3D 1, > + .has_fbc =3D 1, > }; > = > static const struct pci_device_id pciidlist[] =3D { /* aka */ > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_= reg.h > index 5e91fbb..cb8e213 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -849,6 +849,12 @@ > #define SNB_CPU_FENCE_ENABLE (1<<29) > #define DPFC_CPU_FENCE_OFFSET 0x100104 > = > +/* Framebuffer compression for Haswell */ > +#define HSW_FBC_RT_BASE 0x7020 > +#define HSW_FBC_RT_BASE_ADDR_SHIFT 12 > + > +#define HSW_DPFC_CTL_FENCE_EN (1<<28) > +#define HSW_DPFC_CTL_DISABLE_SLB_INIT (1<<15) > = > /* > * GPIO regs > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel= _pm.c > index 27f94cd..94e1c3a 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -253,6 +253,43 @@ static bool ironlake_fbc_enabled(struct drm_device *= dev) > return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; > } > = > +static void haswell_enable_fbc(struct drm_crtc *crtc, unsigned long inte= rval) > +{ > + struct drm_device *dev =3D crtc->dev; > + struct drm_i915_private *dev_priv =3D dev->dev_private; > + struct drm_framebuffer *fb =3D crtc->fb; > + struct intel_framebuffer *intel_fb =3D to_intel_framebuffer(fb); > + struct drm_i915_gem_object *obj =3D intel_fb->obj; > + struct intel_crtc *intel_crtc =3D to_intel_crtc(crtc); > + int plane =3D intel_crtc->plane =3D=3D 0 ? DPFC_CTL_PLANEA : DPFC_CTL_P= LANEB; > + unsigned long stall_watermark =3D 200; > + u32 dpfc_ctl; > + > + dpfc_ctl =3D I915_READ(ILK_DPFC_CONTROL); > + dpfc_ctl |=3D (plane | DPFC_CTL_LIMIT_1X); Accroding to BSpec FBC is always tied to plane A. Bit 30 is MBZ. Maybe fix up plane C FBC support for IVB while you're poking at the general direction? > + dpfc_ctl |=3D (HSW_DPFC_CTL_FENCE_EN | obj->fence_reg); The CPU fence field must be written with 0. SNB/IVB could do with the same fix. > + dpfc_ctl |=3D HSW_DPFC_CTL_DISABLE_SLB_INIT; > + I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | > + (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | > + (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); > + I915_WRITE(HSW_FBC_RT_BASE, > + obj->gtt_offset << HSW_FBC_RT_BASE_ADDR_SHIFT | > + ILK_FBC_RT_VALID); > + /* enable it... */ > + I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); > + > + if (obj->fence_reg !=3D I915_FENCE_REG_NONE) { > + I915_WRITE(SNB_DPFC_CTL_SA, > + SNB_CPU_FENCE_ENABLE | obj->fence_reg); > + I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); > + } else > + I915_WRITE(SNB_DPFC_CTL_SA, ~SNB_CPU_FENCE_ENABLE); > + > + sandybridge_blit_fbc_update(dev); > + > + DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); > +} > + > bool intel_fbc_enabled(struct drm_device *dev) > { > struct drm_i915_private *dev_priv =3D dev->dev_private; > @@ -4158,7 +4195,12 @@ void intel_init_pm(struct drm_device *dev) > if (I915_HAS_FBC(dev)) { > if (HAS_PCH_SPLIT(dev)) { > dev_priv->display.fbc_enabled =3D ironlake_fbc_enabled; > - dev_priv->display.enable_fbc =3D ironlake_enable_fbc; > + if (IS_HASWELL(dev)) > + dev_priv->display.enable_fbc =3D > + haswell_enable_fbc; > + else > + dev_priv->display.enable_fbc =3D > + ironlake_enable_fbc; > dev_priv->display.disable_fbc =3D ironlake_disable_fbc; > } else if (IS_GM45(dev)) { > dev_priv->display.fbc_enabled =3D g4x_fbc_enabled; > -- = > 1.8.1.4 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC