From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 3/3] drm/i915: HSW FBC WaFbcDisableDpfcClockGating Date: Tue, 9 Apr 2013 11:37:57 +0300 Message-ID: <20130409083757.GK4469@intel.com> References: <1365457784-3412-1-git-send-email-rodrigo.vivi@gmail.com> <1365457784-3412-4-git-send-email-rodrigo.vivi@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 5E5DEE5C59 for ; Tue, 9 Apr 2013 01:38:01 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1365457784-3412-4-git-send-email-rodrigo.vivi@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Rodrigo Vivi Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Mon, Apr 08, 2013 at 06:49:44PM -0300, Rodrigo Vivi wrote: > Display register 46500h bit 23 must be set to 1b for the entire time that > Frame Buffer Compression is enabled. So should we enable it again after FBC is disabled to avoid wasting power? > = > Signed-off-by: Rodrigo Vivi > --- > drivers/gpu/drm/i915/i915_reg.h | 3 +++ > drivers/gpu/drm/i915/intel_pm.c | 2 ++ > 2 files changed, 5 insertions(+) > = > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_= reg.h > index 2340bc2..2ef0292 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -863,6 +863,9 @@ > _HSW_PIPE_SLICE_CHICKEN_1_A, + \ > _HSW_PIPE_SLICE_CHICKEN_1_B) > = > +#define HSW_CLKGATE_DISABLE_PART_1 0x46500 > +#define HSW_DPFC_GATING_DISABLE (1<<23) > + > /* > * GPIO regs > */ > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel= _pm.c > index 0628a84..f2ce541 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -281,6 +281,8 @@ static void haswell_enable_fbc(struct drm_crtc *crtc,= unsigned long interval) > /* WaFbcAsynchFlipDisableFbcQueue */ > I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe), > HSW_BYPASS_FBC_QUEUE); > + /* WaFbcDisableDpfcClockGating */ > + I915_WRITE(HSW_CLKGATE_DISABLE_PART_1, HSW_DPFC_GATING_DISABLE); > = > if (obj->fence_reg !=3D I915_FENCE_REG_NONE) { > I915_WRITE(SNB_DPFC_CTL_SA, > -- = > 1.8.1.4 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC